From e9e6db4299ce027921e76ad8212f401be21feeeb Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 7 Jan 2022 10:44:50 +0800 Subject: [PATCH] arch: xtensa: fix unaligned pointer in irq dispatcher In 8186 mtk dsp (hifi5), we meet a system exception when irq is rasied. The panic is LoadStoreAlignmentCause. We found the problem is in int-xxx-dispatcher.S mov a11, a1 addi a11, a11, UEXC_cp1 xchal_cp1_store a11, a12, a13, a14, a15 In xchal_cp1_store macro, ptr must a certain byte aligned address In the 8186 mtk dsp Xtensa header, we have /* * Macro to store the state of TIE coprocessor AudioEngineLX. * Required parameters: * ptr Save area pointer address register (clobbered) * (register must contain a 16 byte aligned address). * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS * registers are clobbered, the remaining are unused). * Optional parameters are the same as for xchal_ncp_store. */ .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 In xtruntime-frames.h, the UEXC_cp1 macro is STRUCT_AFIELD (long,4,UEXC_,cp1, XCHAL_CP1_SA_SIZE / 4) I have checked history and found the original UEXC_cp1 define is using STRUCT_AFIELD. (After 3e1eebe) In 8186 mtk dsp, we need 16 aligned address in xchal_cp1_store using STRUCT_AFIELD_A with XCHAL_TOTAL_SA_ALIGN. --- src/arch/xtensa/include/xtensa/xtruntime-frames.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/xtensa/include/xtensa/xtruntime-frames.h b/src/arch/xtensa/include/xtensa/xtruntime-frames.h index f54911f37..0b6e0d181 100644 --- a/src/arch/xtensa/include/xtensa/xtruntime-frames.h +++ b/src/arch/xtensa/include/xtensa/xtruntime-frames.h @@ -117,10 +117,10 @@ STRUCT_FIELD (long,4,UEXC_,acchi) STRUCT_AFIELD(long,4,UEXC_,mr, 4) #endif #if (XCHAL_CP_MASK & CP0_MASK) -STRUCT_AFIELD (long,4,UEXC_,cp0, XCHAL_CP0_SA_SIZE / 4) +STRUCT_AFIELD_A (long,4,XCHAL_TOTAL_SA_ALIGN,UEXC_,cp0, XCHAL_CP0_SA_SIZE / 4) #endif #if (XCHAL_CP_MASK & CP1_MASK) -STRUCT_AFIELD (long,4,UEXC_,cp1, XCHAL_CP1_SA_SIZE / 4) +STRUCT_AFIELD_A (long,4,XCHAL_TOTAL_SA_ALIGN,UEXC_,cp1, XCHAL_CP1_SA_SIZE / 4) #endif /* ALIGNPAD is the 16-byte alignment padding. */ #define ALIGNPAD ((2 + XCHAL_HAVE_MAC16*2 + ((XCHAL_CP0_SA_SIZE%16)/4) + ((XCHAL_CP1_SA_SIZE%16)/4)) & 3)