mirror of https://github.com/thesofproject/sof.git
uapi: ipc: start moving SSP-specific fields into ssp structure
sample_valid_bits remains in main structure for now since it is handled with a generic dai token. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
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fbcbe586d0
commit
e7fd644c5e
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@ -622,18 +622,26 @@ static int dai_config(struct comp_dev *dev, struct sof_ipc_dai_config *config)
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{
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struct dai_data *dd = comp_get_drvdata(dev);
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/* set dma burst elems to slot number */
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dd->config.burst_elems = config->tdm_slots;
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switch (config->type) {
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case SOF_DAI_INTEL_SSP:
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/* set dma burst elems to slot number */
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dd->config.burst_elems = config->ssp.tdm_slots;
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/* calc frame bytes */
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switch (config->sample_valid_bits) {
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case 16:
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dev->frame_bytes = 2 * config->tdm_slots;
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break;
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case 17 ... 32:
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dev->frame_bytes = 4 * config->tdm_slots;
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/* calc frame bytes */
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switch (config->sample_valid_bits) {
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case 16:
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dev->frame_bytes = 2 * config->ssp.tdm_slots;
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break;
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case 17 ... 32:
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dev->frame_bytes = 4 * config->ssp.tdm_slots;
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break;
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default:
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break;
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}
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break;
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default:
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/* other types of DAIs not handled for now */
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trace_dai_error("de2");
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break;
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}
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@ -168,10 +168,10 @@ static inline int ssp_set_config(struct dai *dai,
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ssto = 0x0;
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/* sstsa dynamic setting is TTSA, default 2 slots */
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sstsa = config->tx_slots;
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sstsa = config->ssp.tx_slots;
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/* ssrsa dynamic setting is RTSA, default 2 slots */
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ssrsa = config->rx_slots;
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ssrsa = config->ssp.rx_slots;
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/* clock masters */
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sscr1 &= ~SSCR1_SFRMDIR;
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@ -259,14 +259,14 @@ static inline int ssp_set_config(struct dai *dai,
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#endif
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/* BCLK is generated from MCLK - must be divisable */
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if (config->mclk_rate % config->bclk_rate) {
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if (config->ssp.mclk_rate % config->ssp.bclk_rate) {
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trace_ssp_error("ec5");
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ret = -EINVAL;
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goto out;
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}
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/* divisor must be within SCR range */
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mdiv = (config->mclk_rate / config->bclk_rate) - 1;
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mdiv = (config->ssp.mclk_rate / config->ssp.bclk_rate) - 1;
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if (mdiv > (SSCR0_SCR_MASK >> 8)) {
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trace_ssp_error("ec6");
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ret = -EINVAL;
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@ -277,7 +277,7 @@ static inline int ssp_set_config(struct dai *dai,
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sscr0 |= SSCR0_SCR(mdiv);
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/* calc frame width based on BCLK and rate - must be divisable */
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if (config->bclk_rate % config->fsync_rate) {
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if (config->ssp.bclk_rate % config->ssp.fsync_rate) {
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trace_ssp_error("ec7");
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ret = -EINVAL;
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goto out;
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@ -285,15 +285,15 @@ static inline int ssp_set_config(struct dai *dai,
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/* must be enough BCLKs for data */
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bdiv = config->bclk_rate / config->fsync_rate;
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if (bdiv < config->tdm_slot_width * config->tdm_slots) {
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bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate;
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if (bdiv < config->ssp.tdm_slot_width * config->ssp.tdm_slots) {
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trace_ssp_error("ec8");
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ret = -EINVAL;
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goto out;
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}
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/* tdm_slot_width must be <= 38 for SSP */
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if (config->tdm_slot_width > 38) {
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if (config->ssp.tdm_slot_width > 38) {
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trace_ssp_error("ec9");
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ret = -EINVAL;
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goto out;
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@ -305,7 +305,7 @@ static inline int ssp_set_config(struct dai *dai,
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start_delay = 1;
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sscr0 |= SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
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if (bdiv % 2) {
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trace_ssp_error("eca");
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@ -331,7 +331,7 @@ static inline int ssp_set_config(struct dai *dai,
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start_delay = 0;
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sscr0 |= SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots);
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/* LJDFD enable */
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sscr2 &= ~SSCR2_LJDFD;
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@ -358,7 +358,7 @@ static inline int ssp_set_config(struct dai *dai,
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start_delay = 0;
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
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/* set asserted frame length */
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frame_len = 1;
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@ -372,15 +372,15 @@ static inline int ssp_set_config(struct dai *dai,
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sspsp |= SSPSP_SFRMP(!inverted_frame);
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sspsp |= SSPSP_FSRT;
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active_tx_slots = hweight_32(config->tx_slots);
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active_rx_slots = hweight_32(config->rx_slots);
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active_tx_slots = hweight_32(config->ssp.tx_slots);
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active_rx_slots = hweight_32(config->ssp.rx_slots);
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break;
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case SOF_DAI_FMT_DSP_B:
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start_delay = 0;
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
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/* set asserted frame length */
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frame_len = 1;
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@ -393,8 +393,8 @@ static inline int ssp_set_config(struct dai *dai,
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*/
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sspsp |= SSPSP_SFRMP(!inverted_frame);
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active_tx_slots = hweight_32(config->tx_slots);
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active_rx_slots = hweight_32(config->rx_slots);
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active_tx_slots = hweight_32(config->ssp.tx_slots);
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active_rx_slots = hweight_32(config->ssp.rx_slots);
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break;
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default:
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@ -406,7 +406,7 @@ static inline int ssp_set_config(struct dai *dai,
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sspsp |= SSPSP_STRTDLY(start_delay);
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sspsp |= SSPSP_SFRMWDTH(frame_len);
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bdiv_min = config->tdm_slots * config->sample_valid_bits;
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bdiv_min = config->ssp.tdm_slots * config->sample_valid_bits;
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if (bdiv < bdiv_min) {
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trace_ssp_error("ecc");
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ret = -EINVAL;
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@ -264,14 +264,14 @@ static inline int ssp_set_config(struct dai *dai,
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#endif
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/* BCLK is generated from MCLK - must be divisable */
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if (config->mclk_rate % config->bclk_rate) {
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if (config->ssp.mclk_rate % config->ssp.bclk_rate) {
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trace_ssp_error("ec5");
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ret = -EINVAL;
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goto out;
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}
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/* divisor must be within SCR range */
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mdiv = (config->mclk_rate / config->bclk_rate) - 1;
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mdiv = (config->ssp.mclk_rate / config->ssp.bclk_rate) - 1;
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if (mdiv > (SSCR0_SCR_MASK >> 8)) {
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trace_ssp_error("ec6");
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ret = -EINVAL;
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@ -282,23 +282,23 @@ static inline int ssp_set_config(struct dai *dai,
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sscr0 |= SSCR0_SCR(mdiv);
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/* calc frame width based on BCLK and rate - must be divisable */
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if (config->bclk_rate % config->fsync_rate) {
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if (config->ssp.bclk_rate % config->ssp.fsync_rate) {
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trace_ssp_error("ec7");
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ret = -EINVAL;
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goto out;
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}
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/* must be enouch BCLKs for data */
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bdiv = config->bclk_rate / config->fsync_rate;
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if (bdiv < config->tdm_slot_width *
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config->tdm_slots) {
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bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate;
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if (bdiv < config->ssp.tdm_slot_width *
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config->ssp.tdm_slots) {
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trace_ssp_error("ec8");
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ret = -EINVAL;
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goto out;
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}
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/* tdm_slot_width must be <= 38 for SSP */
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if (config->tdm_slot_width > 38) {
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if (config->ssp.tdm_slot_width > 38) {
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trace_ssp_error("ec9");
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ret = -EINVAL;
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goto out;
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@ -314,7 +314,7 @@ static inline int ssp_set_config(struct dai *dai,
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sscr3 |= SSCR3_I2S_MODE_EN | SSCR3_I2S_TX_EN | SSCR3_I2S_RX_EN;
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/* set asserted frame length */
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frame_len = config->tdm_slot_width;
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frame_len = config->ssp.tdm_slot_width;
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/* handle frame polarity, I2S default is falling/active low */
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sspsp |= SSPSP_SFRMP(!inverted_frame);
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sscr3 |= SSCR3_I2S_MODE_EN | SSCR3_I2S_TX_EN | SSCR3_I2S_RX_EN;
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/* set asserted frame length */
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frame_len = config->tdm_slot_width;
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frame_len = config->ssp.tdm_slot_width;
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/* LEFT_J default is rising/active high, opposite of I2S */
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sspsp |= SSPSP_SFRMP(inverted_frame);
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@ -369,7 +369,7 @@ static inline int ssp_set_config(struct dai *dai,
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start_delay = 1;
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
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/* set asserted frame length */
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frame_len = 1;
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@ -386,18 +386,18 @@ static inline int ssp_set_config(struct dai *dai,
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* deasserted time of frame)
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*/
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if (cbs)
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sscr4 |= SSCR4_TOT_FRM_PRD(config->tdm_slots *
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config->tdm_slot_width);
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sscr4 |= SSCR4_TOT_FRM_PRD(config->ssp.tdm_slots *
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config->ssp.tdm_slot_width);
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active_tx_slots = hweight_32(config->tx_slots);
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active_rx_slots = hweight_32(config->rx_slots);
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active_tx_slots = hweight_32(config->ssp.tx_slots);
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active_rx_slots = hweight_32(config->ssp.rx_slots);
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break;
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case SOF_DAI_FMT_DSP_B:
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start_delay = 0;
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->tdm_slots);
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sscr0 |= SSCR0_MOD | SSCR0_FRDC(config->ssp.tdm_slots);
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/* set asserted frame length */
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frame_len = 1;
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* deasserted time of frame
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*/
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if (cbs)
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sscr4 |= SSCR4_TOT_FRM_PRD(config->tdm_slots *
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config->tdm_slot_width);
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sscr4 |= SSCR4_TOT_FRM_PRD(config->ssp.tdm_slots *
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config->ssp.tdm_slot_width);
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active_tx_slots = hweight_32(config->tx_slots);
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active_rx_slots = hweight_32(config->rx_slots);
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active_tx_slots = hweight_32(config->ssp.tx_slots);
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active_rx_slots = hweight_32(config->ssp.rx_slots);
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break;
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default:
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@ -454,8 +454,8 @@ static inline int ssp_set_config(struct dai *dai,
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ssp_write(dai, SSCR5, sscr5);
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ssp_write(dai, SSPSP, sspsp);
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ssp_write(dai, SFIFOTT, sfifott);
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ssp_write(dai, SSTSA, config->tx_slots);
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ssp_write(dai, SSRSA, config->rx_slots);
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ssp_write(dai, SSTSA, config->ssp.tx_slots);
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ssp_write(dai, SSRSA, config->ssp.rx_slots);
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ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE;
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ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE;
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@ -231,6 +231,30 @@ struct sof_ipc_dai_ssp_params {
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struct sof_ipc_hdr hdr;
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uint16_t mode; // FIXME: do we need this?
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uint16_t clk_id; // FIXME: do we need this?
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uint32_t mclk_rate; /* mclk frequency in Hz */
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uint32_t fsync_rate; /* fsync frequency in Hz */
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uint32_t bclk_rate; /* bclk frequency in Hz */
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/* TDM */
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uint32_t tdm_slots;
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uint32_t rx_slots;
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uint32_t tx_slots;
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/* data */
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uint16_t tdm_slot_width;
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uint16_t reserved2; /* alignment */
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/* MCLK */
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uint32_t mclk_direction;
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uint32_t mclk_keep_active;
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uint32_t bclk_keep_active;
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uint32_t fs_keep_active;
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//uint32_t quirks; // FIXME: is 32 bits enough ?
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/* private data, e.g. for quirks */
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//uint32_t pdata[10]; // FIXME: would really need ~16 u32
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} __attribute__((packed));
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/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
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@ -255,30 +279,7 @@ struct sof_ipc_dai_config {
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uint16_t format; /* SOF_DAI_FMT_ */
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uint16_t reserved; /* alignment */
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uint32_t mclk_rate; /* mclk frequency in Hz */
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uint32_t fsync_rate; /* fsync frequency in Hz */
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uint32_t bclk_rate; /* bclk frequency in Hz */
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/* TDM */
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uint32_t tdm_slots;
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uint32_t rx_slots;
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uint32_t tx_slots;
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/* data */
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uint32_t sample_valid_bits;
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uint16_t tdm_slot_width;
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uint16_t reserved2; /* alignment */
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/* MCLK */
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uint32_t mclk_direction;
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uint32_t mclk_keep_active;
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uint32_t bclk_keep_active;
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uint32_t fs_keep_active;
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//uint32_t quirks; // FIXME: is 32 bits enough ?
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/* private data, e.g. for quirks */
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//uint32_t pdata[10]; // FIXME: would really need ~16 u32
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/* HW specific data */
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union {
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