mirror of https://github.com/thesofproject/sof.git
panic: Improve panic reporting to include DSP regs and stack dump
Improve the output from panic to include DSP registers and stack dump. Export panic codes to UAPI for host driver logging. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood
parent
f09ce2a6a0
commit
e52ce68347
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@ -33,9 +33,41 @@
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#define __INCLUDE_ARCH_REEF__
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#include <stdint.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include <string.h>
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#include <stdio.h>
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#include <execinfo.h>
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/* architecture specific stack frames to dump */
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#define ARCH_STACK_DUMP_FRAMES 32
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#define arch_memcpy(dest, src, size) \
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memcpy(dest, src, size)
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static inline void *arch_get_stack_ptr(void)
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{
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void *frames[ARCH_STACK_DUMP_FRAMES];
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size_t frame_count;
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size_t i;
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char **symbols;
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frame_count = backtrace(frames, ARCH_STACK_DUMP_FRAMES);
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symbols = backtrace_symbols(frames, frame_count);
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fprintf(stderr, "Dumping %zd stack frames.\n", frame_count);
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for (i = 0; i < frame_count; i++)
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fprintf(stderr, "\t%s\n", symbols[i]);
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free(symbols);
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return NULL;
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}
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static inline void *arch_dump_regs(void)
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{
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return NULL;
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}
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#endif
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@ -190,7 +190,7 @@ void boot_pri_core(void)
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platform_trace_point(TRACE_BOOT_LDR_HPSRAM);
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result = hp_sram_init();
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if (result < 0) {
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platform_panic(PANIC_MEM);
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platform_panic(SOF_IPC_PANIC_MEM);
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return;
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}
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@ -34,15 +34,20 @@
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#include <stdint.h>
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#include <stddef.h>
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#include <reef/mailbox.h>
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#include <uapi/ipc.h>
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/* architecture specific stack frames to dump */
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#define ARCH_STACK_DUMP_FRAMES 32
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void *xthal_memcpy(void *dst, const void *src, size_t len);
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#define arch_memcpy(dest, src, size) \
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xthal_memcpy(dest, src, size)
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static inline size_t arch_get_stack_ptr(void)
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static inline void *arch_get_stack_ptr(void)
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{
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size_t ptr;
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void *ptr;
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/* stack pointer is in a1 */
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__asm__ __volatile__ ("mov %0, a1"
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@ -52,4 +57,58 @@ static inline size_t arch_get_stack_ptr(void)
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return ptr;
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}
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static inline void *arch_dump_regs(void)
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{
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struct sof_ipc_dsp_oops_xtensa *x =
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(struct sof_ipc_dsp_oops_xtensa *) mailbox_get_exception_base();
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/* Exception Vector number - 0x0 */
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__asm__ __volatile__ ("rsr %0, EXCCAUSE" : "=a" (x->exccause) : : "memory");
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/* Exception Vector address - 0x4 */
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__asm__ __volatile__ ("rsr %0, EXCVADDR" : "=a" (x->excvaddr) : : "memory");
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/* Exception Processor State - 0x8 */
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__asm__ __volatile__ ("rsr %0, PS" : "=a" (x->ps) : : "memory");
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/* Level 1 Exception PC - 0xc */
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__asm__ __volatile__ ("rsr %0, EPC1" : "=a" (x->epc1) : : "memory");
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/* Level 2 Exception PC - 0x10 */
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__asm__ __volatile__ ("rsr %0, EPC2" : "=a" (x->epc2) : : "memory");
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/* Level 3 Exception PC - 0x14 */
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__asm__ __volatile__ ("rsr %0, EPC3" : "=a" (x->epc3) : : "memory");
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/* Level 4 Exception PC - 0x18 */
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__asm__ __volatile__ ("rsr %0, EPC4" : "=a" (x->epc4) : : "memory");
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/* Level 5 Exception PC - 0x1c */
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__asm__ __volatile__ ("rsr %0, EPC5" : "=a" (x->epc5) : : "memory");
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/* Level 6 Exception PC - 0x20 */
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__asm__ __volatile__ ("rsr %0, EPC6" : "=a" (x->epc6) : : "memory");
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/* Level 7 Exception PC - 0x24 */
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__asm__ __volatile__ ("rsr %0, EPC7" : "=a" (x->epc7) : : "memory");
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/* Level 2 Exception PS - 0x28 */
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__asm__ __volatile__ ("rsr %0, EPS2" : "=a" (x->eps2) : : "memory");
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/* Level 3 Exception PS - 0x2c */
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__asm__ __volatile__ ("rsr %0, EPS3" : "=a" (x->eps3) : : "memory");
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/* Level 4 Exception PS - 0x30 */
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__asm__ __volatile__ ("rsr %0, EPS4" : "=a" (x->eps4) : : "memory");
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/* Level 5 Exception PS - 0x34 */
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__asm__ __volatile__ ("rsr %0, EPS5" : "=a" (x->eps5) : : "memory");
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/* Level 6 Exception PS - 0x38 */
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__asm__ __volatile__ ("rsr %0, EPS6" : "=a" (x->eps6) : : "memory");
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/* Level 7 Exception PS - 0x3c */
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__asm__ __volatile__ ("rsr %0, EPS7" : "=a" (x->eps7) : : "memory");
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/* Double Exception program counter - 0x40 */
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__asm__ __volatile__ ("rsr %0, DEPC" : "=a" (x->depc) : : "memory");
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/* Interrupts Enabled - 0x44 */
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__asm__ __volatile__ ("rsr %0, INTENABLE" : "=a" (x->intenable) : : "memory");
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/* Interrupts Status - 0x48 */
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__asm__ __volatile__ ("rsr %0, INTERRUPT" : "=a" (x->interrupt) : : "memory");
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/* Shift register - 0x4c */
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__asm__ __volatile__ ("rsr %0, SAR" : "=a" (x->sar) : : "memory");
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/* Register A1 (stack) - 0x50 */
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__asm__ __volatile__ ("mov %0, a1" : "=a" (x->stack) : : "memory");
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dcache_writeback_region((void *)x, sizeof(*x));
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/* tell caller extended data can be placed hereafter */
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return (void *)(x + 1);
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}
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#endif
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@ -35,7 +35,7 @@
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#include <platform/interrupt.h>
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#include <reef/mailbox.h>
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#include <arch/task.h>
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#include <reef/debug.h>
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#include <reef/panic.h>
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#include <reef/init.h>
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#include <reef/lock.h>
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#include <stdint.h>
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@ -45,92 +45,11 @@ uint32_t lock_dbg_atomic = 0;
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uint32_t lock_dbg_user[DBG_LOCK_USERS] = {0};
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#endif
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/* TODO: this should be fixed by rotating the register Window on the stack and
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* dumping the saved registers.
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* TODO: we should also have different handlers for each type where we can take
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* advantage of dumping further information. i.e. call stack and avoid
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* clobbering some registers dumped below are clobbered */
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static void exception(void)
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{
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volatile uint32_t *dump = (uint32_t*) mailbox_get_exception_base();
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/* Exception Vector number - 0x0 */
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__asm__ __volatile__ ("rsr %0, EXCCAUSE" : "=a" (dump[0]) : : "memory");
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/* Exception Vector address - 0x4 */
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__asm__ __volatile__ ("rsr %0, EXCVADDR" : "=a" (dump[1]) : : "memory");
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/* Exception Processor State - 0x8 */
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__asm__ __volatile__ ("rsr %0, PS" : "=a" (dump[2]) : : "memory");
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/* Level 1 Exception PC - 0xc */
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__asm__ __volatile__ ("rsr %0, EPC1" : "=a" (dump[3]) : : "memory");
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/* Level 2 Exception PC - 0x10 */
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__asm__ __volatile__ ("rsr %0, EPC2" : "=a" (dump[4]) : : "memory");
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/* Level 3 Exception PC - 0x14 */
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__asm__ __volatile__ ("rsr %0, EPC3" : "=a" (dump[5]) : : "memory");
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/* Level 4 Exception PC - 0x18 */
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__asm__ __volatile__ ("rsr %0, EPC4" : "=a" (dump[6]) : : "memory");
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/* Level 5 Exception PC - 0x1c */
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__asm__ __volatile__ ("rsr %0, EPC5" : "=a" (dump[7]) : : "memory");
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/* Level 6 Exception PC - 0x20 */
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__asm__ __volatile__ ("rsr %0, EPC6" : "=a" (dump[8]) : : "memory");
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/* Level 7 Exception PC - 0x24 */
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__asm__ __volatile__ ("rsr %0, EPC7" : "=a" (dump[9]) : : "memory");
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/* Level 2 Exception PS - 0x28 */
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__asm__ __volatile__ ("rsr %0, EPS2" : "=a" (dump[10]) : : "memory");
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/* Level 3 Exception PS - 0x2c */
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__asm__ __volatile__ ("rsr %0, EPS3" : "=a" (dump[11]) : : "memory");
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/* Level 4 Exception PS - 0x30 */
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__asm__ __volatile__ ("rsr %0, EPS4" : "=a" (dump[12]) : : "memory");
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/* Level 5 Exception PS - 0x34 */
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__asm__ __volatile__ ("rsr %0, EPS5" : "=a" (dump[13]) : : "memory");
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/* Level 6 Exception PS - 0x38 */
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__asm__ __volatile__ ("rsr %0, EPS6" : "=a" (dump[14]) : : "memory");
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/* Level 7 Exception PS - 0x3c */
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__asm__ __volatile__ ("rsr %0, EPS7" : "=a" (dump[15]) : : "memory");
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/* Double Exception program counter - 0x40 */
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__asm__ __volatile__ ("rsr %0, DEPC" : "=a" (dump[16]) : : "memory");
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/* Register A0 - 0x44 */
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__asm__ __volatile__ ("mov %0, a0" : "=a" (dump[17]) : : "memory");
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/* Register A1 - 0x48 */
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__asm__ __volatile__ ("mov %0, a1" : "=a" (dump[18]) : : "memory");
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/* Register A2 - 0x4c */
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__asm__ __volatile__ ("mov %0, a2" : "=a" (dump[19]) : : "memory");
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/* Register A3 - 0x50 */
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__asm__ __volatile__ ("mov %0, a3" : "=a" (dump[20]) : : "memory");
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/* Register A4 - 0x54 */
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__asm__ __volatile__ ("mov %0, a4" : "=a" (dump[21]) : : "memory");
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/* Register A5 - 0x58 */
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__asm__ __volatile__ ("mov %0, a5" : "=a" (dump[22]) : : "memory");
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/* Register A6 - 0x5c */
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__asm__ __volatile__ ("mov %0, a6" : "=a" (dump[23]) : : "memory");
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/* Register A7 - 0x60 */
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__asm__ __volatile__ ("mov %0, a7" : "=a" (dump[24]) : : "memory");
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/* Register A8 - 0x64 */
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__asm__ __volatile__ ("mov %0, a8" : "=a" (dump[25]) : : "memory");
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/* Register A9 - 0x68 */
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__asm__ __volatile__ ("mov %0, a9" : "=a" (dump[26]) : : "memory");
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/* Register A10 - 0x6c */
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__asm__ __volatile__ ("mov %0, a10" : "=a" (dump[27]) : : "memory");
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/* Register A11 - 0x70 */
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__asm__ __volatile__ ("mov %0, a11" : "=a" (dump[28]) : : "memory");
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/* Register A12 - 0x74 */
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__asm__ __volatile__ ("mov %0, a12" : "=a" (dump[29]) : : "memory");
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/* Register A13 - 0x78 */
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__asm__ __volatile__ ("mov %0, a13" : "=a" (dump[30]) : : "memory");
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/* Register A14 - 0x7c */
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__asm__ __volatile__ ("mov %0, a14" : "=a" (dump[31]) : : "memory");
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/* Register A15 - 0x80 */
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__asm__ __volatile__ ("mov %0, a15" : "=a" (dump[32]) : : "memory");
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/* Interrupts Enabled - 0x84 */
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__asm__ __volatile__ ("rsr %0, INTENABLE" : "=a" (dump[33]) : : "memory");
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/* Interrupts Status - 0x88 */
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__asm__ __volatile__ ("rsr %0, INTERRUPT" : "=a" (dump[34]) : : "memory");
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/* Shift register - 0x8c */
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__asm__ __volatile__ ("rsr %0, SAR" : "=a" (dump[35]) : : "memory");
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/* atm we loop forever */
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/* TODO: we should probably stall/HALT at this point or recover */
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panic(PANIC_EXCEPTION);
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/* now panic and rewind 8 stack frames. */
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/* TODO: we could invoke a GDB stub here */
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panic_rewind(SOF_IPC_PANIC_EXCEPTION, 8 * sizeof(uint32_t));
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}
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static void register_exceptions(void)
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@ -23,6 +23,7 @@ include_HEADERS = \
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lock.h \
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mailbox.h \
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notifier.h \
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panic.h \
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reef.h \
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schedule.h \
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ssp.h \
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@ -32,22 +32,13 @@
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#ifndef __INCLUDE_DEBUG__
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#define __INCLUDE_DEBUG__
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#include <reef/reef.h>
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#include <reef/mailbox.h>
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#include <uapi/ipc.h>
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#include <platform/platform.h>
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#include <stdint.h>
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#include <stdlib.h>
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/* panic reasons */
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#define PANIC_MEM 0
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#define PANIC_WORK 1
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#define PANIC_IPC 2
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#define PANIC_ARCH 3
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#define PANIC_PLATFORM 4
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#define PANIC_TASK 5
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#define PANIC_EXCEPTION 6
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#define PANIC_DEADLOCK 7
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#define PANIC_STACK 8
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#define PANIC_IDLE 9
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#define DEBUG
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@ -136,38 +127,31 @@
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#define dump_object_ptr(__o)
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#endif
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/* panic and stop executing any more code */
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#define panic(_p) \
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do { \
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interrupt_global_disable(); \
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dbg_val(0xdead0000 | _p) \
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platform_panic(_p); \
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while(1) {}; \
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} while (0);
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/* dump stack as part of panic */
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#define panic_dump_stack(_p) \
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do { \
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extern uint32_t __stack; \
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extern uint32_t _stack_sentry; \
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uint32_t _stack_bottom = (uint32_t)&__stack; \
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uint32_t _stack_limit = (uint32_t)&_stack_sentry; \
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uint32_t _stack_top = arch_get_stack_ptr(); \
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uint32_t _size = _stack_bottom - _stack_top; \
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uint32_t _panic = _p; \
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dbg_val(0xdead0000 | _p) \
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dbg_val_at(_stack_top, 1) \
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dbg_val_at(_stack_bottom, 2) \
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/* is stack smashed ? */\
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if (_stack_bottom <= _stack_limit) { \
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dbg_val_at(0x51ac0000 | _p, 3); \
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_stack_bottom = _stack_limit; \
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_panic = PANIC_STACK; \
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} \
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platform_panic(_panic); \
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dump_at(_stack_top, (_size - sizeof(uint32_t)) >> 2, 4) \
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\
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while(1) {}; \
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} while (0);
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static inline void dump_stack(uint32_t p, void *addr, size_t offset,
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size_t limit)
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{
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extern void *__stack;
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extern void *_stack_sentry;
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void *stack_bottom = (void *)&__stack;
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void *stack_limit = (void *)&_stack_sentry;
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void *stack_top = arch_get_stack_ptr() + offset;
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size_t size = stack_bottom - stack_top;
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/* is stack smashed ? */
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if (stack_top - offset <= stack_limit) {
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stack_bottom = stack_limit;
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p = SOF_IPC_PANIC_STACK;
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platform_panic(p);
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}
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/* make sure stack size won't overflow dump area */
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if (size > limit)
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size = limit;
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/* copy stack contents and writeback */
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rmemcpy(addr, stack_top, size - sizeof(void *));
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dcache_writeback_region(addr, size - sizeof(void *));
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}
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#endif
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@ -116,7 +116,7 @@ extern uint32_t lock_dbg_user[DBG_LOCK_USERS];
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trace_lock_error("DED"); \
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trace_lock_value(__LINE__); \
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trace_lock_value((lock)->user); \
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panic(PANIC_DEADLOCK); /* lock not acquired */ \
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panic(SOF_IPC_PANIC_DEADLOCK); /* lock not acquired */ \
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} \
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} while (0);
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@ -0,0 +1,69 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#ifndef __INCLUDE_SOF_IPC_PANIC__
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#define __INCLUDE_SOF_IPC_PANIC__
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#include <reef/reef.h>
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#include <reef/mailbox.h>
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#include <reef/interrupt.h>
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#include <platform/platform.h>
|
||||
#include <uapi/ipc.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
/* panic and rewind stack */
|
||||
static inline void panic_rewind(uint32_t p, uint32_t stack_rewind_frames)
|
||||
{
|
||||
void *ext_offset;
|
||||
|
||||
/* disable all IRQs */
|
||||
interrupt_global_disable();
|
||||
|
||||
/* dump DSP core registers */
|
||||
ext_offset = arch_dump_regs();
|
||||
|
||||
/* dump stack frames */
|
||||
dump_stack(SOF_IPC_PANIC_EXCEPTION, ext_offset, stack_rewind_frames,
|
||||
ARCH_STACK_DUMP_FRAMES * sizeof(uint32_t));
|
||||
|
||||
/* TODO: send IPC oops message to host */
|
||||
|
||||
/* panic and loop forever */
|
||||
platform_panic(p);
|
||||
while (1) {};
|
||||
}
|
||||
|
||||
static inline void panic(uint32_t p)
|
||||
{
|
||||
panic_rewind(p, 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -126,6 +126,23 @@
|
|||
/* maximum message size for mailbox Tx/Tx */
|
||||
#define SOF_IPC_MSG_MAX_SIZE 128
|
||||
|
||||
/*
|
||||
* SOF panic codes
|
||||
*/
|
||||
#define SOF_IPC_PANIC_MAGIC 0x0dead000
|
||||
#define SOF_IPC_PANIC_MAGIC_MASK 0x0ffff000
|
||||
#define SOF_IPC_PANIC_CODE_MASK 0x00000fff
|
||||
#define SOF_IPC_PANIC_MEM (SOF_IPC_PANIC_MAGIC | 0)
|
||||
#define SOF_IPC_PANIC_WORK (SOF_IPC_PANIC_MAGIC | 1)
|
||||
#define SOF_IPC_PANIC_IPC (SOF_IPC_PANIC_MAGIC | 2)
|
||||
#define SOF_IPC_PANIC_ARCH (SOF_IPC_PANIC_MAGIC | 3)
|
||||
#define SOF_IPC_PANIC_PLATFORM (SOF_IPC_PANIC_MAGIC | 4)
|
||||
#define SOF_IPC_PANIC_TASK (SOF_IPC_PANIC_MAGIC | 5)
|
||||
#define SOF_IPC_PANIC_EXCEPTION (SOF_IPC_PANIC_MAGIC | 6)
|
||||
#define SOF_IPC_PANIC_DEADLOCK (SOF_IPC_PANIC_MAGIC | 7)
|
||||
#define SOF_IPC_PANIC_STACK (SOF_IPC_PANIC_MAGIC | 8)
|
||||
#define SOF_IPC_PANIC_IDLE (SOF_IPC_PANIC_MAGIC | 9)
|
||||
|
||||
/*
|
||||
* Command Header - Header for all IPC. Identifies IPC message.
|
||||
* The size can be greater than the structure size and that means there is
|
||||
|
|
@ -820,4 +837,33 @@ struct sof_ipc_dma_trace_posn {
|
|||
uint32_t messages; /* total trace messages */
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Architecture specific debug
|
||||
*/
|
||||
|
||||
/* Xtensa Firmware Oops data */
|
||||
struct sof_ipc_dsp_oops_xtensa {
|
||||
uint32_t exccause;
|
||||
uint32_t excvaddr;
|
||||
uint32_t ps;
|
||||
uint32_t epc1;
|
||||
uint32_t epc2;
|
||||
uint32_t epc3;
|
||||
uint32_t epc4;
|
||||
uint32_t epc5;
|
||||
uint32_t epc6;
|
||||
uint32_t epc7;
|
||||
uint32_t eps2;
|
||||
uint32_t eps3;
|
||||
uint32_t eps4;
|
||||
uint32_t eps5;
|
||||
uint32_t eps6;
|
||||
uint32_t eps7;
|
||||
uint32_t depc;
|
||||
uint32_t intenable;
|
||||
uint32_t interrupt;
|
||||
uint32_t sar;
|
||||
uint32_t stack;
|
||||
} __attribute__((packed));
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include <reef/init.h>
|
||||
#include <reef/task.h>
|
||||
#include <reef/debug.h>
|
||||
#include <reef/panic.h>
|
||||
#include <reef/alloc.h>
|
||||
#include <reef/notifier.h>
|
||||
#include <reef/work.h>
|
||||
|
|
@ -59,7 +60,7 @@ int main(int argc, char *argv[])
|
|||
trace_point(TRACE_BOOT_ARCH);
|
||||
err = arch_init(&reef);
|
||||
if (err < 0)
|
||||
panic(PANIC_ARCH);
|
||||
panic(SOF_IPC_PANIC_ARCH);
|
||||
|
||||
/* initialise system services */
|
||||
trace_point(TRACE_BOOT_SYS_HEAP);
|
||||
|
|
@ -76,7 +77,7 @@ int main(int argc, char *argv[])
|
|||
/* init the platform */
|
||||
err = platform_init(&reef);
|
||||
if (err < 0)
|
||||
panic(PANIC_PLATFORM);
|
||||
panic(SOF_IPC_PANIC_PLATFORM);
|
||||
|
||||
trace_point(TRACE_BOOT_PLATFORM);
|
||||
|
||||
|
|
@ -84,6 +85,6 @@ int main(int argc, char *argv[])
|
|||
err = do_task(&reef);
|
||||
|
||||
/* should never get here */
|
||||
panic_dump_stack(PANIC_TASK);
|
||||
panic(SOF_IPC_PANIC_TASK);
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include <reef/reef.h>
|
||||
#include <reef/agent.h>
|
||||
#include <reef/debug.h>
|
||||
#include <reef/panic.h>
|
||||
#include <reef/alloc.h>
|
||||
#include <reef/clock.h>
|
||||
#include <reef/trace.h>
|
||||
|
|
@ -70,7 +71,7 @@ static uint64_t validate(void *data, uint64_t delay)
|
|||
if (delta > sa->ticks) {
|
||||
trace_sa("tim");
|
||||
trace_sa_value(delta);
|
||||
panic_dump_stack(PANIC_IDLE);
|
||||
panic(SOF_IPC_PANIC_IDLE);
|
||||
}
|
||||
|
||||
return PLATFORM_IDLE_TIME;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <reef/alloc.h>
|
||||
#include <reef/reef.h>
|
||||
#include <reef/debug.h>
|
||||
#include <reef/panic.h>
|
||||
#include <reef/trace.h>
|
||||
#include <reef/lock.h>
|
||||
#include <platform/memory.h>
|
||||
|
|
@ -216,7 +217,7 @@ static void *rmalloc_sys(size_t bytes)
|
|||
memmap.system.heap += bytes;
|
||||
if (memmap.system.heap >= HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) {
|
||||
trace_mem_error("eMd");
|
||||
panic(PANIC_MEM);
|
||||
panic(SOF_IPC_PANIC_MEM);
|
||||
}
|
||||
|
||||
#if DEBUG_BLOCK_ALLOC
|
||||
|
|
|
|||
|
|
@ -50,5 +50,6 @@
|
|||
/* IPC page data copy timeout */
|
||||
#define PLATFORM_IPC_DMA_TIMEOUT 2000
|
||||
|
||||
static inline void platform_panic(uint32_t p) {}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ int do_task(struct reef *reef)
|
|||
/* init static pipeline */
|
||||
pdata.p = init_static_pipeline();
|
||||
if (pdata.p == NULL)
|
||||
panic(PANIC_TASK);
|
||||
panic(SOF_IPC_PANIC_TASK);
|
||||
#endif
|
||||
/* let host know DSP boot is complete */
|
||||
platform_boot_complete(0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue