mirror of https://github.com/thesofproject/sof.git
cht: Add M/N dividers for 19.2MHz
Add some M/N divider entries for 19.2M source clock. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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@ -100,12 +100,17 @@ struct ssp_mn {
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uint32_t n;
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};
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/* TODO: move over to the PLL instead of M/N */
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static const struct ssp_mn ssp_mn_conf[] = {
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{25000000, 24, 48000, 1152, 25000}, /* 1.152MHz */
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{25000000, 32, 48000, 1536, 25000}, /* 1.536MHz */
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{25000000, 64, 48000, 3072, 25000}, /* 3.072MHz */
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{25000000, 400, 48000, 96, 125}, /* 19.2MHz */
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{25000000, 400, 44100, 441, 625}, /* 17.64MHz */
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{19200000, 24, 48000, 3, 50}, /* 1.152MHz */
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{19200000, 32, 48000, 2, 25}, /* 1.536MHz */
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{19200000, 64, 48000, 4, 25}, /* 3.072MHz */
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{19200000, 400, 44100, 441, 480}, /* 17.64MHz */
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};
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/* set the SSP M/N clock dividers */
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