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topology: set DMIC pipe with eq-iir with 40 Hz highpass 

For headset playback or capture, default pipe is volume. If The high pass
filter is required to prevent HDA codec headset glitches, it can be set by
HSMICPROC=eq-iir-volume. It use use 40 Hz high pass filter with +0 db
boost. If there is DMIC, this set default pipe as eq-iir, which use
the same 40 Hz high-pass filter too. For DMIC16K, 40 Hz high-pass for 16khz
version filter is used.

Default coefficient for FIR/IIR is changed fr m coef flat to coef pass.
Pass configuration has the advantage of low system load.
    eq_fir_coef_flat.m4 to eq_fir_coef_pass.m4
    eq_iir_coef_flat.m4 to eq_iir_coef_pass.m4

Below pipe files are renamed for naming convention,
    pipe-eq-volume-playback.m4 -> pipe-eq-iir-eq-fir-volume-playback.m4
    pipe-eq-capture-16khz.m4 -> pipe-eq-iir-volume-capture-16khz.m4
    pipe-eq-capture.m4 -> pipe-eq-iir-volume-capture.m4

Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
This commit is contained in:
Fred Oh 2020-04-02 18:41:39 -07:00 committed by Liam Girdwood
parent 8b49743a20
commit d65495e984
12 changed files with 111 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
tools/topology/CMakeLists.txt
View File

@ -26,8 +26,8 @@ set(TPLGS
"sof-hda-generic\;sof-hda-generic\;-DCHANNELS=0\;-DPPROC=volume"
"sof-hda-generic\;sof-hda-generic-2ch\;-DCHANNELS=2\;-DPPROC=volume"
"sof-hda-generic\;sof-hda-generic-4ch\;-DCHANNELS=4\;-DPPROC=volume"
"sof-hda-generic\;sof-hda-generic-eq-2ch\;-DCHANNELS=2\;-DPPROC=eq-volume"
"sof-hda-generic\;sof-hda-generic-eq-4ch\;-DCHANNELS=4\;-DPPROC=eq-volume"
"sof-hda-generic\;sof-hda-generic-eq-2ch\;-DCHANNELS=2\;-DPPROC=eq-iir-eq-fir-volume"
"sof-hda-generic\;sof-hda-generic-eq-4ch\;-DCHANNELS=4\;-DPPROC=eq-iir-eq-fir-volume"
"sof-hda-generic-kwd\;sof-hda-generic-2ch-kwd\;-DCHANNELS=2"
"sof-hda-generic-kwd\;sof-hda-generic-4ch-kwd\;-DCHANNELS=4"
"sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0"
@ -74,11 +74,11 @@ set(TPLGS
"sof-apl-da7219\;sof-apl-da7219"
"sof-glk-da7219-kwd\;sof-glk-da7219-kwd"
"sof-glk-da7219\;sof-glk-da7219"
"sof-glk-da7219\;sof-glk-eq-da7219\;-DDMICPROC=eq"
"sof-glk-da7219\;sof-glk-eq-da7219\;-DDMICPROC=eq-iir-volume"
"sof-glk-rt5682\;sof-glk-rt5682"
"sof-icl-nocodec\;sof-icl-nocodec"
"sof-apl-pcm512x-nohdmi\;sof-apl-eq-pcm512x\;-DPPROC=eq-volume"
"sof-apl-dmic\;sof-apl-eq-dmic\;-DCHANNELS=4\;-DCPROC=eq"
"sof-apl-pcm512x-nohdmi\;sof-apl-eq-pcm512x\;-DPPROC=eq-iir-eq-fir-volume"
"sof-apl-dmic\;sof-apl-eq-dmic\;-DCHANNELS=4\;-DCPROC=eq-iir-volume"
"sof-apl-src-dmic\;sof-apl-src-dmic"
"sof-apl-dmic-asymmetric\;sof-apl-dmic-a2ch-b4ch\;-DDMICSETTING=apl-dmic-a2b4"
"sof-apl-dmic-asymmetric\;sof-apl-dmic-a2ch-b2ch\;-DDMICSETTING=apl-dmic-a2b2"
@ -99,7 +99,7 @@ set(TPLGS
"sof-apl-src-pcm512x\;sof-apl-src-pcm512x"
"sof-cml-rt5682\;sof-cml-rt5682\;-DPLATFORM=cml"
"sof-cml-rt5682\;sof-cml-eq-fir-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume"
"sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER1=eq_fir_coef_loudness.m4"
"sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume\;-DPIPELINE_FILTER1=eq_iir_coef_loudness.m4\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER2=eq_fir_coef_loudness.m4"
"sof-cml-rt5682\;sof-cml-eq-iir-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume"
"sof-cml-rt5682\;sof-whl-rt5682\;-DPLATFORM=whl"
"sof-cml-rt5682\;sof-icl-rt5682\;-DPLATFORM=icl"
@ -113,7 +113,7 @@ set(TPLGS
"sof-cml-rt5682-max98357a\;sof-cml-rt5682-max98357a\;-DPLATFORM=cml"
"sof-cml-demux-rt5682-max98357a\;sof-cml-demux-rt5682-max98357a\;-DPLATFORM=cml"
"sof-cml-rt1011-rt5682\;sof-cml-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=volume"
"sof-cml-rt1011-rt5682\;sof-cml-eq-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=eq-volume"
"sof-cml-rt1011-rt5682\;sof-cml-eq-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=eq-iir-eq-fir-volume"
"sof-tgl-nocodec\;sof-tgl-nocodec"
"sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308\;-DHDMI=1"
"sof-tgl-rt711-i2s-rt1308\;sof-tgl-rt711-i2s-rt1308-nohdmi"

4
tools/topology/platform/intel/intel-generic-dmic.m4
View File

@ -21,14 +21,14 @@ dnl time_domain, sched_comp)
# Passthrough capture pipeline using max channels defined by CHANNELS.
# Set 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4,
PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC_DAI_LINK_48k_ID, CHANNELS, s32le,
1000, 0, 0, 48000, 48000, 48000)
# Passthrough capture pipeline using max channels defined by CHANNELS.
# Schedule with 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4,
PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture-16khz.m4,
DMIC_PIPELINE_16k_ID, DMIC_DAI_LINK_16k_ID, CHANNELS, s32le,
1000, 0, 0, 16000, 16000, 16000)

4
tools/topology/sof-apl-pcm512x.m4
View File

@ -79,14 +79,14 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
# DMIC passthrough capture pipeline 7 on PCM 4 using max 2 channels.
# 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4,
PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture.m4,
7, 5, 4, s32le,
1000, 0, 0,
48000, 48000, 48000)
# DMIC16kHz passthrough capture pipeline 8 on PCM 5 using max 2 channels.
# 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4,
PIPELINE_PCM_ADD(sof/pipe-eq-iir-volume-capture-16khz.m4,
8, 6, 2, s16le,
1000, 0, 0,
16000, 16000, 16000)

4
tools/topology/sof-cml-rt5682.m4
View File

@ -22,8 +22,8 @@ DEBUG_START
# if XPROC is not defined, define with default pipe
ifdef(`HSMICPROC', , `define(HSMICPROC, volume)')
ifdef(`HSEARPROC', , `define(HSEARPROC, volume)')
ifdef(`DMICPROC', , `define(DMICPROC, passthrough)')
ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, volume)')
ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)')
ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)')
#
# Define the pipelines

6
tools/topology/sof/pipe-eq-fir-capture.m4
View File

@ -20,8 +20,8 @@ include(`eq_fir.m4')
define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID))
define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID))
# define filter. eq_fir_coef_flat.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)')
# define filter. eq_fir_coef_pass.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)')
include(PIPELINE_FILTER2)
# EQ Bytes control with max value of 255
@ -54,7 +54,7 @@ W_BUFFER(0, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP)
W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP)

4
tools/topology/sof/pipe-eq-fir-playback.m4
View File

@ -20,8 +20,8 @@ include(`eq_fir.m4')
define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID))
define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID))
# define filter. eq_fir_coef_flat.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)')
# define filter. eq_fir_coef_pass.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)')
include(PIPELINE_FILTER2)
# EQ Bytes control with max value of 255

4
tools/topology/sof/pipe-eq-fir-volume-capture.m4
View File

@ -49,8 +49,8 @@ W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS)
define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID))
define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID))
# define filter. eq_fir_coef_flat.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)')
# define filter. eq_fir_coef_pass.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)')
include(PIPELINE_FILTER2)
# EQ Bytes control with max value of 255

4
tools/topology/sof/pipe-eq-fir-volume-playback.m4
View File

@ -43,8 +43,8 @@ W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS)
define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID))
define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID))
# EQ initial parameters, in this case flat response
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_flat.m4)')
# define filter. eq_fir_coef_pass.m4 is set by default
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)')
include(PIPELINE_FILTER2)
# EQ Bytes control with max value of 255

2
tools/topology/sof/pipe-eq-iir-capture.m4
View File

@ -54,7 +54,7 @@ W_BUFFER(0, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP)
W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
W_BUFFER(1, COMP_BUFFER_SIZE(DAI_PERIODS,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS,
COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP)

53
tools/topology/sof/pipe-eq-volume-playback.m4 → tools/topology/sof/pipe-eq-iir-eq-fir-volume-playback.m4
View File

@ -33,35 +33,54 @@ C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID,
# Volume configuration
#
W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens,
define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID))
define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID))
W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens,
LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"'
` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"'))
W_DATA(playback_pga_conf, playback_pga_tokens)
W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS)
# Use coefficients for flat frequency response
include(`eq_iir_coef_flat.m4')
#
# IIR EQ
#
define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
# By default, use coefficients for pass frequency response
ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_pass.m4)')
include(PIPELINE_FILTER1)
# EQ Bytes control with max value of 255
C_CONTROLBYTES(EQIIR, PIPELINE_ID,
C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
, , ,
CONTROLBYTES_MAX(, 304),
,
EQIIR_priv)
DEF_EQIIR_PRIV)
# Use coefficients for flat frequency response
include(`eq_fir_coef_flat.m4')
#
# FIR EQ
#
define(DEF_EQFIR_COEF, concat(`eqfir_coef_', PIPELINE_ID))
define(DEF_EQFIR_PRIV, concat(`eqfir_priv_', PIPELINE_ID))
# By default, use coefficients for pass frequency response
ifdef(`PIPELINE_FILTER2', , `define(PIPELINE_FILTER2, eq_fir_coef_pass.m4)')
include(PIPELINE_FILTER2)
# EQ Bytes control with max value of 255
C_CONTROLBYTES(EQFIR, PIPELINE_ID,
C_CONTROLBYTES(DEF_EQFIR_COEF, PIPELINE_ID,
CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
, , ,
CONTROLBYTES_MAX(, 4096),
,
EQFIR_priv)
DEF_EQFIR_PRIV)
#
# Components and Buffers
@ -72,13 +91,17 @@ C_CONTROLBYTES(EQFIR, PIPELINE_ID,
W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0)
# "Volume" has 2 source and x sink periods
W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume"))
W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF, LIST(` ', "PIPELINE_ID Master Playback Volume"))
# "EQ 0" has 2 sink period and 2 source periods
W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQIIR"))
W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQIIR_COEF"))
# "EQ 0" has 2 sink period and 2 source periods
W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "EQFIR"))
W_EQ_FIR(0, PIPELINE_FORMAT, 2, 2, LIST(` ', "DEF_EQFIR_COEF"))
# "Volume" has x sink and 2 source periods
W_PGA(0, PIPELINE_FORMAT, DAI_PERIODS, 2, DEF_PGA_CONF,
LIST(` ', "PIPELINE_ID Master Playback Volume"))
# Playback Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(2,
@ -121,3 +144,7 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_I
#
PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE, PCM_MAX_RATE, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
undefine(`DEF_PGA_TOKENS')
undefine(`DEF_PGA_CONF')
undefine(`DEF_EQIIR_COEF')
undefine(`DEF_EQIIR_PRIV')

29
tools/topology/sof/pipe-eq-capture-16khz.m4 → tools/topology/sof/pipe-eq-iir-volume-capture-16khz.m4
View File

@ -33,17 +33,25 @@ C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID,
LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
# Volume Configuration
W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens,
define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID))
define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID))
W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens,
LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"'
` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"'))
W_DATA(capture_pga_conf, capture_pga_tokens)
W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS)
# Use 50 Hz highpass response with +20 dB gain
include(`eq_iir_coef_highpass_50hz_20db_16khz.m4')
define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
# By default, use 40 Hz highpass response with +0 dB gain for 16khz
# TODO: need to implement middle level macro handler per pipeline
ifdef(`DMIC16KPROC_FILTER1', , `define(DMIC16KPROC_FILTER1, eq_iir_coef_highpass_40hz_0db_16khz.m4)')
include(DMIC16KPROC_FILTER1)
# EQ Bytes control with max value of 255
C_CONTROLBYTES(EQIIR_C16, PIPELINE_ID,
C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
CONTROLBYTES_OPS(bytes,
258 binds the mixer control to bytes get/put handlers,
258, 258),
@ -53,7 +61,7 @@ C_CONTROLBYTES(EQIIR_C16, PIPELINE_ID,
, , ,
CONTROLBYTES_MAX(, 304),
,
EQIIR_HP50HZ20dB16K_priv)
DEF_EQIIR_PRIV)
#
# Components and Buffers
@ -65,11 +73,11 @@ W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2)
# "Volume" has 2 source and 2 sink periods
W_PGA(0, PIPELINE_FORMAT, 2, 2,
capture_pga_conf, LIST(` ',
DEF_PGA_CONF, LIST(` ',
"CONTROL_NAME"))
# "EQ 0" has 2 sink period and x source periods
W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "EQIIR_C16"))
W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "DEF_EQIIR_COEF"))
# Capture Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(2,
@ -112,3 +120,8 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', 16000, 16000,
PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
undefine(`DEF_PGA_TOKENS')
undefine(`DEF_PGA_CONF')
undefine(`DEF_EQIIR_COEF')
undefine(`DEF_EQIIR_PRIV')

40
tools/topology/sof/pipe-eq-capture.m4 → tools/topology/sof/pipe-eq-iir-volume-capture.m4
View File

@ -18,14 +18,14 @@ include(`eq_iir.m4')
define(`PGA_NAME', Dmic0)
define(`CONTROL_NAME_VOLUME', Capture Volume)
define(`CONTROL_NAME_SWITCH', Capture Switch)
define(`CONTROL_NAME', `CONTROL_NAME_VOLUME')
define(`CONTROL_NAME', `PIPELINE_ID CONTROL_NAME_VOLUME')
#
# Controls
#
# Volume Mixer control with max value of 32
C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID,
C_CONTROLMIXER(Capture Volume, PIPELINE_ID,
CONTROLMIXER_OPS(volsw,
256 binds the mixer control to volume get/put handlers,
256, 256),
@ -35,10 +35,11 @@ C_CONTROLMIXER(Master Capture Volume, PIPELINE_ID,
Channel register and shift for Front Left/Right,
LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
define(`CONTROL_NAME', `CONTROL_NAME_SWITCH')
undefine(`CONTROL_NAME')
define(`CONTROL_NAME', `PIPELINE_ID CONTROL_NAME_SWITCH')
# Switch type Mixer Control with max value of 1
C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID,
C_CONTROLMIXER(Capture Switch, PIPELINE_ID,
CONTROLMIXER_OPS(volsw, 259 binds the mixer control to switch get/put handlers, 259, 259),
CONTROLMIXER_MAX(max 1 indicates switch type control, 1),
false,
@ -48,17 +49,25 @@ C_CONTROLMIXER(Master Capture Switch, PIPELINE_ID,
"1", "1")
# Volume Configuration
W_VENDORTUPLES(capture_pga_tokens, sof_volume_tokens,
define(DEF_PGA_TOKENS, concat(`pga_tokens_', PIPELINE_ID))
define(DEF_PGA_CONF, concat(`pga_conf_', PIPELINE_ID))
W_VENDORTUPLES(DEF_PGA_TOKENS, sof_volume_tokens,
LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"'
` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"'))
W_DATA(capture_pga_conf, capture_pga_tokens)
W_DATA(DEF_PGA_CONF, DEF_PGA_TOKENS)
# Use 50 Hz highpass response with +20 dB gain
include(`eq_iir_coef_highpass_50hz_20db_48khz.m4')
define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
# By default, use 40 Hz highpass response with +0 dB gain for 48khz
# TODO: need to implement middle level macro handler per pipeline
ifdef(`DMICPROC_FILTER1', , `define(DMICPROC_FILTER1, eq_iir_coef_highpass_40hz_0db_48khz.m4)')
include(DMICPROC_FILTER1)
# EQ Bytes control with max value of 255
C_CONTROLBYTES(EQIIR_C48, PIPELINE_ID,
C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
CONTROLBYTES_OPS(bytes,
258 binds the mixer control to bytes get/put handlers,
258, 258),
@ -68,7 +77,7 @@ C_CONTROLBYTES(EQIIR_C48, PIPELINE_ID,
, , ,
CONTROLBYTES_MAX(, 304),
,
EQIIR_HP50HZ20dB48K_priv)
DEF_EQIIR_PRIV)
#
# Components and Buffers
@ -80,11 +89,11 @@ W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2)
# "Volume" has 2 source and 2 sink periods
W_PGA(0, PIPELINE_FORMAT, 2, 2,
capture_pga_conf, LIST(` ',
"CONTROL_NAME_VOLUME", "CONTROL_NAME_SWITCH"))
DEF_PGA_CONF, LIST(` ',
"PIPELINE_ID CONTROL_NAME_VOLUME", "PIPELINE_ID CONTROL_NAME_SWITCH"))
# "EQ 0" has 2 sink period and x source periods
W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "EQIIR_C48"))
W_EQ_IIR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, LIST(` ', "DEF_EQIIR_COEF"))
# Capture Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(2,
@ -130,3 +139,8 @@ indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
PCM_CAPABILITIES(Highpass Capture PCM_ID, `S32_LE,S24_LE,S16_LE', PCM_MIN_RATE,
PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS,
2, 16, 192, 16384, 65536, 65536)
undefine(`DEF_PGA_TOKENS')
undefine(`DEF_PGA_CONF')
undefine(`DEF_EQIIR_COEF')
undefine(`DEF_EQIIR_PRIV')