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interrupt: remove unmask parameter 

Removes unmask parameter from interrupt structures and functions.
It's not been used for a long time now.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda 2019-10-04 14:30:24 +02:00 committed by Daniel Baluta
parent 0f2315fba8
commit d1f4320988
12 changed files with 20 additions and 47 deletions
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3
src/drivers/imx/ipc.c
View File

@ -175,8 +175,7 @@ int platform_ipc_init(struct ipc *ipc)
#endif
/* configure interrupt */
interrupt_register(PLATFORM_IPC_INTERRUPT, IRQ_AUTO_UNMASK,
irq_handler, _ipc);
interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, _ipc);
interrupt_enable(PLATFORM_IPC_INTERRUPT, _ipc);
/* enable GP #0 for Host -> DSP message notification

3
src/drivers/intel/baytrail/ipc.c
View File

@ -199,8 +199,7 @@ int platform_ipc_init(struct ipc *ipc)
iipc->dh_buffer.dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
/* configure interrupt */
interrupt_register(PLATFORM_IPC_INTERRUPT, IRQ_AUTO_UNMASK,
irq_handler, ipc);
interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, ipc);
interrupt_enable(PLATFORM_IPC_INTERRUPT, ipc);
/* Unmask Busy and Done interrupts */

3
src/drivers/intel/cavs/dmic.c
View File

@ -1537,8 +1537,7 @@ static int dmic_probe(struct dai *dai)
return ret;
}
ret = interrupt_register(dmic->irq, IRQ_AUTO_UNMASK,
dmic_irq_handler, dai);
ret = interrupt_register(dmic->irq, dmic_irq_handler, dai);
if (ret < 0) {
trace_dmic_error("dmic failed to allocate IRQ");
rfree(dmic);

3
src/drivers/intel/cavs/idc.c
View File

@ -379,8 +379,7 @@ int idc_init(void)
PLATFORM_IDC_INTERRUPT_NAME);
if ((*idc)->irq < 0)
return (*idc)->irq;
ret = interrupt_register((*idc)->irq, IRQ_AUTO_UNMASK, idc_irq_handler,
*idc);
ret = interrupt_register((*idc)->irq, idc_irq_handler, *idc);
if (ret < 0)
return ret;
interrupt_enable((*idc)->irq, *idc);

2
src/drivers/intel/cavs/ipc.c
View File

@ -233,7 +233,7 @@ int platform_ipc_init(struct ipc *ipc)
PLATFORM_IPC_INTERRUPT_NAME);
if (irq < 0)
return irq;
interrupt_register(irq, IRQ_AUTO_UNMASK, ipc_irq_handler, ipc);
interrupt_register(irq, ipc_irq_handler, ipc);
interrupt_enable(irq, ipc);
/* enable IPC interrupts from host */

3
src/drivers/intel/cavs/timer.c
View File

@ -107,8 +107,7 @@ static int platform_timer_register(struct timer *timer,
if (timer->logical_irq < 0)
return timer->logical_irq;
err = interrupt_register(timer->logical_irq, IRQ_MANUAL_UNMASK, handler,
arg);
err = interrupt_register(timer->logical_irq, handler, arg);
if (err < 0)
return err;

3
src/drivers/intel/haswell/ipc.c
View File

@ -189,8 +189,7 @@ int platform_ipc_init(struct ipc *ipc)
iipc->dh_buffer.dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED);
/* configure interrupt */
interrupt_register(PLATFORM_IPC_INTERRUPT, IRQ_AUTO_UNMASK,
irq_handler, ipc);
interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, ipc);
interrupt_enable(PLATFORM_IPC_INTERRUPT, ipc);
/* Unmask Busy and Done interrupts */

3
src/drivers/intel/pmc-ipc.c
View File

@ -137,8 +137,7 @@ int platform_ipc_pmc_init(void)
sizeof(struct intel_ipc_pmc_data));
/* configure interrupt */
interrupt_register(IRQ_NUM_EXT_PMC, IRQ_AUTO_UNMASK, irq_handler,
_pmc);
interrupt_register(IRQ_NUM_EXT_PMC, irq_handler, _pmc);
interrupt_enable(IRQ_NUM_EXT_PMC, _pmc);
/* Unmask Busy and Done interrupts */

28
src/drivers/interrupt.c
View File

@ -26,8 +26,7 @@ static union {
uint8_t bytes[PLATFORM_DCACHE_ALIGN];
} cascade_root;
static int interrupt_register_internal(uint32_t irq, int unmask,
void (*handler)(void *arg),
static int interrupt_register_internal(uint32_t irq, void (*handler)(void *arg),
void *arg, struct irq_desc *desc);
static void interrupt_unregister_internal(uint32_t irq, const void *arg,
struct irq_desc *desc);
@ -149,7 +148,7 @@ void interrupt_init(void)
}
static int irq_register_child(struct irq_cascade_desc *cascade, int irq,
int unmask, void (*handler)(void *arg), void *arg,
void (*handler)(void *arg), void *arg,
struct irq_desc *desc)
{
unsigned int core = cpu_get_id();
@ -173,12 +172,6 @@ static int irq_register_child(struct irq_cascade_desc *cascade, int irq,
irq);
return -EEXIST;
}
if (child->unmask != unmask) {
trace_error(TRACE_CLASS_IRQ,
"error: IRQ 0x%x flags differ!", irq);
return -EINVAL;
}
}
if (!desc) {
@ -198,15 +191,12 @@ static int irq_register_child(struct irq_cascade_desc *cascade, int irq,
child->cpu_mask = 0;
}
child->unmask = unmask;
list_item_append(&child->irq_list, head);
/* do we need to register parent on this CPU? */
if (!cascade->num_children[core])
ret = interrupt_register_internal(parent->irq, IRQ_AUTO_UNMASK,
parent->handler, parent,
parent);
ret = interrupt_register_internal(parent->irq, parent->handler,
parent, parent);
/* increment number of children */
if (!ret)
@ -334,14 +324,12 @@ static uint32_t irq_disable_child(struct irq_cascade_desc *cascade, int irq,
return 0;
}
int interrupt_register(uint32_t irq, int unmask, void (*handler)(void *arg),
void *arg)
int interrupt_register(uint32_t irq, void (*handler)(void *arg), void *arg)
{
return interrupt_register_internal(irq, unmask, handler, arg, NULL);
return interrupt_register_internal(irq, handler, arg, NULL);
}
static int interrupt_register_internal(uint32_t irq, int unmask,
void (*handler)(void *arg),
static int interrupt_register_internal(uint32_t irq, void (*handler)(void *arg),
void *arg, struct irq_desc *desc)
{
struct irq_cascade_desc *cascade;
@ -355,7 +343,7 @@ static int interrupt_register_internal(uint32_t irq, int unmask,
return arch_interrupt_register(irq, handler, arg);
spin_lock_irq(cascade->lock, flags);
ret = irq_register_child(cascade, irq, unmask, handler, arg, desc);
ret = irq_register_child(cascade, irq, handler, arg, desc);
spin_unlock_irq(cascade->lock, flags);
return ret;

9
src/include/sof/drivers/interrupt.h
View File

@ -22,9 +22,6 @@
#define trace_irq_error(__e, ...) \
trace_error(TRACE_CLASS_IRQ, __e, ##__VA_ARGS__)
#define IRQ_MANUAL_UNMASK 0
#define IRQ_AUTO_UNMASK 1
/**
* \brief child IRQ descriptor for cascading IRQ controllers.
*/
@ -42,9 +39,6 @@ struct irq_desc {
int irq; /**< virtual IRQ number */
void (*handler)(void *arg); /**< interrupt handler function */
void *handler_arg; /**< interrupt handler argument */
int unmask; /**< whether irq should be
* automatically unmasked
*/
uint32_t cpu_mask; /**< a mask of CPUs on which this
* interrupt is enabled
*/
@ -112,8 +106,7 @@ struct irq_cascade_tmpl {
bool global_mask;
};
int interrupt_register(uint32_t irq, int unmask, void(*handler)(void *arg),
void *arg);
int interrupt_register(uint32_t irq, void(*handler)(void *arg), void *arg);
void interrupt_unregister(uint32_t irq, const void *arg);
uint32_t interrupt_enable(uint32_t irq, void *arg);
uint32_t interrupt_disable(uint32_t irq, void *arg);

4
src/schedule/dma_multi_chan_domain.c
View File

@ -66,8 +66,8 @@ static int dma_multi_chan_domain_irq_register(struct dma_domain_data *data,
/* always go through dma_multi_chan_domain_irq_handler,
* so we have different arg registered for every channel
*/
ret = interrupt_register(data->irq, IRQ_AUTO_UNMASK,
dma_multi_chan_domain_irq_handler, data);
ret = interrupt_register(data->irq, dma_multi_chan_domain_irq_handler,
data);
if (ret < 0)
return ret;

3
src/schedule/edf_schedule.c
View File

@ -280,8 +280,7 @@ int scheduler_init_edf(struct sof *sof)
if (edf_sch->irq < 0)
return edf_sch->irq;
interrupt_register(edf_sch->irq, IRQ_AUTO_UNMASK, edf_scheduler_run,
edf_sch);
interrupt_register(edf_sch->irq, edf_scheduler_run, edf_sch);
interrupt_enable(edf_sch->irq, edf_sch);
return 0;