mirror of https://github.com/thesofproject/sof.git
arch: fix level 1 interrupts handling by slave cores
Fixes handling of level 1 interrupts by slave cores. Level 1 interrupts are handled by UserVector, which for slave cores was set by default to ROM location. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
parent
3b34b60e81
commit
c6cc4cc70d
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@ -168,7 +168,6 @@ xtos_per_core:
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writesr excsave 5 a4
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writesr excsave 5 a4
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#endif
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#endif
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xtos_per_core_cacheattr:
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get_prid a5
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get_prid a5
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#if PLATFORM_MASTER_CORE_ID == 0
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#if PLATFORM_MASTER_CORE_ID == 0
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beqz a5, xtos_per_core_obtain_xtos_structs
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beqz a5, xtos_per_core_obtain_xtos_structs
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@ -176,6 +175,8 @@ xtos_per_core_cacheattr:
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movi a4, PLATFORM_MASTER_CORE_ID
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movi a4, PLATFORM_MASTER_CORE_ID
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beq a5, a4, xtos_per_core_obtain_xtos_structs
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beq a5, a4, xtos_per_core_obtain_xtos_structs
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#endif
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#endif
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xtos_per_core_cacheattr:
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#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || \
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#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || \
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XCHAL_HAVE_XLT_CACHEATTR || \
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XCHAL_HAVE_XLT_CACHEATTR || \
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(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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@ -183,6 +184,13 @@ xtos_per_core_cacheattr:
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cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
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cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
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#endif
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#endif
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xtos_per_core_vecbase:
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#if XCHAL_HAVE_VECBASE
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/* note: absolute symbol, not a ptr */
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movi a2, _memmap_vecbase_reset
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wsr.vecbase a2
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#endif
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// Obtain core structs from given address.
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// Obtain core structs from given address.
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xtos_per_core_obtain_xtos_structs:
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xtos_per_core_obtain_xtos_structs:
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get_prid a5
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get_prid a5
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@ -128,7 +128,7 @@ LABEL(_Level,FromVector):
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// Change stack pointer
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// Change stack pointer
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xtos_stack_addr_percore a13, _INTERRUPT_LEVEL, xtos_stack_for_interrupt
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xtos_stack_addr_percore a13, _INTERRUPT_LEVEL, xtos_stack_for_interrupt
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s32i a1, a13, 0
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s32i a1, a13, 0
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addi a1, a13, XTOS_STACK_FOR_INTERRUPT_SIZE
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addi a1, a13, XTOS_INT_STACK_SIZE
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/* Load the handler from the table, initialize two args (interrupt
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/* Load the handler from the table, initialize two args (interrupt
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* number and exception stack frame), then call the interrupt handler.
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* number and exception stack frame), then call the interrupt handler.
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@ -165,24 +165,10 @@ ENTRY(_MainEntry)
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_rom_store_table = 0;
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_rom_store_table = 0;
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/* ABI0 does not use Window base */
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/* ABI0 does not use Window base */
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PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
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PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
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/* Various memory-map dependent cache attribute settings: */
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x44024000;
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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_memmap_cacheattr_wt_base = 0x11021000;
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_memmap_cacheattr_bp_base = 0x22022000;
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_memmap_cacheattr_unused_mask = 0x00F00FFF;
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_memmap_cacheattr_wb_trapnull = 0x4422422F;
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_memmap_cacheattr_wba_trapnull = 0x4422422F;
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_memmap_cacheattr_wbna_trapnull = 0x25222222;
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_memmap_cacheattr_wt_trapnull = 0x1122122F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0x44F24FFF;
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_memmap_cacheattr_wt_strict = 0x11F21FFF;
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_memmap_cacheattr_bp_strict = 0x22F22FFF;
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_memmap_cacheattr_wb_allvalid = 0x44224222;
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_memmap_cacheattr_wt_allvalid = 0x11221222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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SECTIONS
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SECTIONS
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@ -143,7 +143,7 @@
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#define HEAP_SYSTEM_0_BASE \
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#define HEAP_SYSTEM_0_BASE \
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(SOF_TEXT_BASE + SOF_TEXT_SIZE +\
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(SOF_TEXT_BASE + SOF_TEXT_SIZE +\
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SOF_DATA_SIZE + SOF_BSS_DATA_SIZE)
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SOF_DATA_SIZE + SOF_BSS_DATA_SIZE)
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#define HEAP_SYSTEM_0_SIZE 0x8000
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#define HEAP_SYSTEM_0_SIZE 0xa000
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#define HEAP_SYSTEM_1_BASE (HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_0_SIZE)
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#define HEAP_SYSTEM_1_BASE (HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_0_SIZE)
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#define HEAP_SYSTEM_1_SIZE 0x1000
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#define HEAP_SYSTEM_1_SIZE 0x1000
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@ -161,24 +161,10 @@ ENTRY(_MainEntry)
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_rom_store_table = 0;
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_rom_store_table = 0;
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/* ABI0 does not use Window base */
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/* ABI0 does not use Window base */
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PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
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PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
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/* Various memory-map dependent cache attribute settings: */
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x44024000;
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_memmap_cacheattr_wt_base = 0x11021000;
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_memmap_cacheattr_bp_base = 0x22022000;
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_memmap_cacheattr_unused_mask = 0x00F00FFF;
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_memmap_cacheattr_wb_trapnull = 0x4422422F;
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_memmap_cacheattr_wba_trapnull = 0x4422422F;
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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_memmap_cacheattr_wt_trapnull = 0x1122122F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0x44F24FFF;
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_memmap_cacheattr_wt_strict = 0x11F21FFF;
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_memmap_cacheattr_bp_strict = 0x22F22FFF;
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_memmap_cacheattr_wb_allvalid = 0x44224222;
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_memmap_cacheattr_wt_allvalid = 0x11221222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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SECTIONS
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SECTIONS
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@ -161,24 +161,10 @@ ENTRY(_MainEntry)
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_rom_store_table = 0;
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_rom_store_table = 0;
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/* ABI0 does not use Window base */
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/* ABI0 does not use Window base */
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PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
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PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
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/* Various memory-map dependent cache attribute settings: */
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x44024000;
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_memmap_cacheattr_wt_base = 0x11021000;
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_memmap_cacheattr_bp_base = 0x22022000;
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_memmap_cacheattr_unused_mask = 0x00F00FFF;
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_memmap_cacheattr_wb_trapnull = 0x4422422F;
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_memmap_cacheattr_wba_trapnull = 0x4422422F;
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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_memmap_cacheattr_wt_trapnull = 0x1122122F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0x44F24FFF;
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_memmap_cacheattr_wt_strict = 0x11F21FFF;
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_memmap_cacheattr_bp_strict = 0x22F22FFF;
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_memmap_cacheattr_wb_allvalid = 0x44224222;
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_memmap_cacheattr_wt_allvalid = 0x11221222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
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SECTIONS
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SECTIONS
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