ace: clock: Update clock definitions

Added code with clock definitions

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Signed-off-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>

src/platform/intel/ace/include/ace/lib/clk.h

@@ -39,8 +39,6 @@ struct sof;
 #define NUM_CLOCKS	(CLK_SSP + 1)
 
 extern const struct freq_table *cpu_freq;
-extern const uint32_t cpu_freq_enc[];
-extern const uint32_t cpu_freq_status_mask[];
 
 void platform_clock_init(struct sof *sof);
 

src/platform/intel/ace/lib/clk.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Copyright(c) 2022 Intel Corporation. All rights reserved.
+//
+// Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
+
+#include <sof/lib/notifier.h>
+#include <rtos/clk.h>
+#include <sof/drivers/ssp.h>
+#include <sof/sof.h>
+#include <sof/common.h>
+#include <sof/lib/memory.h>
+#include <rtos/spinlock.h>
+
+static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS];
+
+void platform_clock_init(struct sof *sof)
+{
+	uint32_t platform_lowest_clock = CPU_LOWEST_FREQ_IDX;
+	int i;
+
+	sof->clocks = platform_clocks_info;
+
+	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
+		sof->clocks[i] = (struct clock_info) {
+			.freqs_num = NUM_CPU_FREQ,
+			.freqs = cpu_freq,
+			.default_freq_idx = CPU_DEFAULT_IDX,
+			.current_freq_idx = CPU_DEFAULT_IDX,
+			.lowest_freq_idx = platform_lowest_clock,
+			.notification_id = NOTIFIER_ID_CPU_FREQ,
+			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
+		};
+
+		k_spinlock_init(&sof->clocks[i].lock);
+	}
+}

src/platform/intel/ace/platform.c

@@ -73,6 +73,9 @@ int platform_boot_complete(uint32_t boot_message)
 /* Runs on the primary core only */
 int platform_init(struct sof *sof)
 {
+	trace_point(TRACE_BOOT_PLATFORM_CLOCK);
+	platform_clock_init(sof);
+
 	trace_point(TRACE_BOOT_PLATFORM_SCHED);
 	scheduler_init_edf();
 

src/platform/meteorlake/lib/clk.c

@@ -14,22 +14,6 @@ static const struct freq_table platform_cpu_freq[] = {
 	{ CLK_MAX_CPU_HZ, 400000 },
 };
 
-const uint32_t cpu_freq_enc[] = {
+STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);
-	SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST |
-		SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
-	SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING |
-		SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
-	SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING |
-		SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
-};
-
-const uint32_t cpu_freq_status_mask[] = {
-	SHIM_CLKSTS_WOV_CRO,
-	SHIM_CLKSTS_LROSCCS,
-	SHIM_CLKSTS_HROSCCS
-};
-
-STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
-	      invalid_number_of_cpu_frequencies);
 
 const struct freq_table *cpu_freq = platform_cpu_freq;

zephyr/CMakeLists.txt

@@ -438,6 +438,7 @@ if (CONFIG_ACE_VERSION_1_5)
 		${SOF_PLATFORM_PATH}/intel/ace/platform.c
 		${SOF_PLATFORM_PATH}/meteorlake/lib/clk.c
 		${SOF_PLATFORM_PATH}/intel/ace/lib/pm_runtime.c
+		${SOF_PLATFORM_PATH}/intel/ace/lib/clk.c
 	)
 
 	# SOF core infrastructure - runs on top of Zephyr