From c32a0e032fc04df2edaab0dd1b7f012f9c50d73e Mon Sep 17 00:00:00 2001 From: "fy.tsuo" Date: Mon, 17 May 2021 20:53:06 +0800 Subject: [PATCH] topology: igo_nr: move igo_nr to core 1. igo_nr runs on core 1 to balance loading. Signed-off-by: fy.tsuo --- tools/topology/platform/intel/intel-generic-dmic-kwd.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/topology/platform/intel/intel-generic-dmic-kwd.m4 b/tools/topology/platform/intel/intel-generic-dmic-kwd.m4 index b646a8c31..e0cd58d41 100644 --- a/tools/topology/platform/intel/intel-generic-dmic-kwd.m4 +++ b/tools/topology/platform/intel/intel-generic-dmic-kwd.m4 @@ -68,7 +68,7 @@ define(`PGA_NAME', Dmic0) PIPELINE_PCM_ADD(sof/pipe-`DMICPROC'-capture.m4, DMIC_PIPELINE_48k_ID, DMIC_PCM_48k_ID, CHANNELS, s32le, - INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 0, 48000, 48000, 48000) + INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 1, 48000, 48000, 48000) undefine(`PGA_NAME') undefine(`PIPELINE_FILTER1') @@ -102,7 +102,7 @@ dnl deadline, priority, core, time_domain) DAI_ADD(sof/pipe-dai-capture.m4, DMIC_PIPELINE_48k_ID, DMIC, 0, DMIC_DAI_LINK_48k_NAME, concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le, - INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 1, SCHEDULE_TIME_DOMAIN_TIMER) # capture DAI is DMIC 1 using 3 periods # Buffers use s32le format, with 320 frame per 20000us on core 0 with priority 0