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memory: enable LPSRAM on APL 

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
Marcin Rajwa 2019-04-15 12:46:48 +02:00 committed by Tomasz Lauda
parent 2593efb82b
commit c17de6a979
1 changed files with 15 additions and 6 deletions
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21
src/arch/xtensa/boot_loader.c
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@ -218,15 +218,25 @@ static uint32_t hp_sram_init(void)
#endif #endif
#if defined(CONFIG_ICELAKE) #if defined(CONFIG_APOLLOLAKE)
static int32_t lp_sram_init(void) static int32_t lp_sram_init(void)
{ {
int status; uint32_t status;
unsigned int timeout_counter, delay_count = 256; uint32_t lspgctl_value;
uint32_t timeout_counter, delay_count = 256;
timeout_counter = delay_count; timeout_counter = delay_count;
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON); shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
/* add some delay before writing power registers */
idelay(delay_count);
lspgctl_value = shim_read(LSPGCTL);
shim_write(LSPGCTL, lspgctl_value & !LPSRAM_MASK(0));
/* add some delay before checking the status */
idelay(delay_count);
/* query the power status of first part of LP memory */ /* query the power status of first part of LP memory */
/* to check whether it has been powered up. A few */ /* to check whether it has been powered up. A few */
/* cycles are needed for it to be powered up */ /* cycles are needed for it to be powered up */
@ -236,11 +246,10 @@ static int32_t lp_sram_init(void)
platform_panic(SOF_IPC_PANIC_MEM); platform_panic(SOF_IPC_PANIC_MEM);
break; break;
} }
idelay(delay_count);
status = io_reg_read(LSPGISTS); status = io_reg_read(LSPGISTS);
} }
/* add some extra delay before touch power register */
idelay(delay_count);
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS); shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS);
return status; return status;
@ -263,7 +272,7 @@ void boot_master_core(void)
return; return;
} }
#if defined(CONFIG_ICELAKE) #if defined(CONFIG_APOLLOLAKE)
/* init the LPSRAM */ /* init the LPSRAM */
platform_trace_point(TRACE_BOOT_LDR_LPSRAM); platform_trace_point(TRACE_BOOT_LDR_LPSRAM);