mirror of https://github.com/thesofproject/sof.git
platform: cavs: use pm-runtime api to power gate dsp cores
Power control hw programming should go through the pm_runtime interface. It provides more granular control over the power gating of each single dsp core. Signed-off-by: Marcin Maka <marcin.maka@linux.intel.com>
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@ -48,6 +48,8 @@ void arch_cpu_enable_core(int id)
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irq_local_disable(flags);
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irq_local_disable(flags);
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if (!arch_cpu_is_core_enabled(id)) {
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if (!arch_cpu_is_core_enabled(id)) {
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pm_runtime_get(PM_RUNTIME_DSP, id);
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/* Turn on stack memory for core */
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/* Turn on stack memory for core */
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pm_runtime_get(CORE_MEMORY_POW, id);
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pm_runtime_get(CORE_MEMORY_POW, id);
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@ -133,6 +135,8 @@ void cpu_power_down_core(void)
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/* Turn off stack memory for core */
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/* Turn off stack memory for core */
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pm_runtime_put(CORE_MEMORY_POW, cpu_get_id());
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pm_runtime_put(CORE_MEMORY_POW, cpu_get_id());
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pm_runtime_put(PM_RUNTIME_DSP, cpu_get_id());
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/* arch_wait_for_interrupt() not used, because it will cause panic.
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/* arch_wait_for_interrupt() not used, because it will cause panic.
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* This code is executed on irq lvl > 0, which is expected.
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* This code is executed on irq lvl > 0, which is expected.
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* Core will be put into reset by host anyway.
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* Core will be put into reset by host anyway.
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@ -405,9 +405,7 @@ int platform_init(struct sof *sof)
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shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
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shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
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/* prevent DSP Common power gating */
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/* prevent DSP Common power gating */
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shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSPPG(0) |
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pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);
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SHIM_PWRCTL_TCPDSPPG(1) | SHIM_PWRCTL_TCPDSPPG(2) |
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SHIM_PWRCTL_TCPDSPPG(3));
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#elif CONFIG_ICELAKE || CONFIG_SUECREEK || CONFIG_TIGERLAKE
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#elif CONFIG_ICELAKE || CONFIG_SUECREEK || CONFIG_TIGERLAKE
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/* TODO: need to merge as for APL */
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/* TODO: need to merge as for APL */
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@ -422,9 +420,7 @@ int platform_init(struct sof *sof)
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io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
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io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
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/* prevent DSP Common power gating */
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/* prevent DSP Common power gating */
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shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSPPG(0) |
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pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);
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SHIM_PWRCTL_TCPDSPPG(1) | SHIM_PWRCTL_TCPDSPPG(2) |
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SHIM_PWRCTL_TCPDSPPG(3));
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#endif
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#endif
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/* init DMACs */
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/* init DMACs */
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