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platform: cavs: use pm-runtime api to power gate dsp cores 

Power control hw programming should go through the pm_runtime
interface. It provides more granular control over the power
gating of each single dsp core.

Signed-off-by: Marcin Maka <marcin.maka@linux.intel.com>
This commit is contained in:
Marcin Maka 2019-09-23 20:30:48 +02:00 committed by Liam Girdwood
parent 14dcd128bd
commit b5c8f83c48
2 changed files with 6 additions and 6 deletions
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4
src/arch/xtensa/lib/cpu.c
View File

@ -48,6 +48,8 @@ void arch_cpu_enable_core(int id)
irq_local_disable(flags);
if (!arch_cpu_is_core_enabled(id)) {
pm_runtime_get(PM_RUNTIME_DSP, id);
/* Turn on stack memory for core */
pm_runtime_get(CORE_MEMORY_POW, id);
@ -133,6 +135,8 @@ void cpu_power_down_core(void)
/* Turn off stack memory for core */
pm_runtime_put(CORE_MEMORY_POW, cpu_get_id());
pm_runtime_put(PM_RUNTIME_DSP, cpu_get_id());
/* arch_wait_for_interrupt() not used, because it will cause panic.
* This code is executed on irq lvl > 0, which is expected.
* Core will be put into reset by host anyway.

8
src/platform/intel/cavs/platform.c
View File

@ -405,9 +405,7 @@ int platform_init(struct sof *sof)
shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
/* prevent DSP Common power gating */
shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSPPG(0) |
SHIM_PWRCTL_TCPDSPPG(1) | SHIM_PWRCTL_TCPDSPPG(2) |
SHIM_PWRCTL_TCPDSPPG(3));
pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);
#elif CONFIG_ICELAKE || CONFIG_SUECREEK || CONFIG_TIGERLAKE
/* TODO: need to merge as for APL */
@ -422,9 +420,7 @@ int platform_init(struct sof *sof)
io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
/* prevent DSP Common power gating */
shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSPPG(0) |
SHIM_PWRCTL_TCPDSPPG(1) | SHIM_PWRCTL_TCPDSPPG(2) |
SHIM_PWRCTL_TCPDSPPG(3));
pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);
#endif
/* init DMACs */