From aef421ac4a4eed4f2861cbb7965b7583e0fa5186 Mon Sep 17 00:00:00 2001 From: Pierre-Louis Bossart Date: Sat, 27 Jun 2020 14:16:59 -0500 Subject: [PATCH] topology: cht-max98090: align with byt-nocodec Only the SSP settings need to be different. Signed-off-by: Pierre-Louis Bossart --- tools/topology/CMakeLists.txt | 2 +- tools/topology/sof-cht-max98090.m4 | 77 +++++++++++++++++------------- 2 files changed, 45 insertions(+), 34 deletions(-) diff --git a/tools/topology/CMakeLists.txt b/tools/topology/CMakeLists.txt index a891535b5..7f6693b3c 100644 --- a/tools/topology/CMakeLists.txt +++ b/tools/topology/CMakeLists.txt @@ -20,7 +20,6 @@ set(TPLGS "sof-cht-nocodec\;sof-cht-nocodec\;-DPLATFORM=cht-nocodec\;-DSSP_NUM=2" "sof-cht-nocodec\;sof-byt-nocodec\;-DPLATFORM=byt-nocodec\;-DSSP_NUM=2" "sof-bdw-nocodec\;sof-bdw-nocodec" - "sof-cht-max98090\;sof-cht-max98090" "sof-hda-generic\;sof-hda-generic\;-DCHANNELS=0\;-DPPROC=volume" "sof-hda-generic\;sof-hda-generic-2ch\;-DCHANNELS=2\;-DPPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4" "sof-hda-generic\;sof-hda-generic-4ch\;-DCHANNELS=4\;-DPPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4" @@ -61,6 +60,7 @@ set(TPLGS "sof-byt-codec\;sof-cht-da7213\;-DCODEC=DA7213\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-cx2072x\;-DCODEC=CX2072X\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-es8316\;-DCODEC=ES8316\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" + "sof-cht-max98090\;sof-cht-max98090\;-DCODEC=MAX98090\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-cnl-rt274\;sof-cnl-rt274" "sof-apl-tdf8532\;sof-apl-tdf8532" "sof-apl-pcm512x\;sof-apl-pcm512x\;-DFSYNC=48000" diff --git a/tools/topology/sof-cht-max98090.m4 b/tools/topology/sof-cht-max98090.m4 index 067c12aea..e1f52c5da 100644 --- a/tools/topology/sof-cht-max98090.m4 +++ b/tools/topology/sof-cht-max98090.m4 @@ -1,6 +1,4 @@ -# -# Topology for generic CHT/BSW board with Maxim 98090 codec -# +`# Topology for generic' PLATFORM `board with' CODEC `on SSP' SSP_NUM # Include topology builder include(`utils.m4') @@ -14,26 +12,18 @@ include(`common/tlv.m4') # Include Token library include(`sof/tokens.m4') -# Include Cherrytrail DSP configuration -include(`platform/intel/cht.m4') +# Include DSP configuration +include(`platform/intel/'PLATFORM`.m4') # # Define the pipelines # -# PCM0 ----> volume ---------------+ -# |--low latency mixer ----> volume ----> SSP2 -# PCM1 -----> volume ----> SRC ----+ -# +# PCM0 -----> volume -------v +# low latency mixer ----> volume ----> SSP2 +# PCM1 -----> volume -------^ # PCM0 <---- Volume <---- SSP2 # -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline on core 0 with priority 1 -PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4, - 1, 0, 2, s32le, - 1000, 1, 0, - 48000, 48000, 48000) - # Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. # 1000us deadline on core 0 with priority 0 PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4, @@ -49,43 +39,64 @@ PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4, # playback DAI is SSP2 using 2 periods # Buffers use s16le format, 1000us deadline on core 0 with priority 1 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_1, 2, s16le, - 1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA) +# this defines pipeline 1. The 'NOT_USED_IGNORED' is due to dependencies +# and is adjusted later with an explicit dapm line. +DAI_ADD(sof/pipe-mixer-dai-playback.m4, + 1, SSP, SSP_NUM, SSP2-Codec, + NOT_USED_IGNORED, 2, s16le, + 1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA, + 2, 48000) -# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le. -# 4000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4, - 3, 1, 2, s32le, - 4000, 0, 0, - 8000, 48000, 48000, - 0, PIPELINE_PLAYBACK_SCHED_COMP_1) +# PCM Playback pipeline 3 on PCM 0 using max 2 channels of s32le. +# 1000us deadline on core 0 with priority 0 +# this is connected to pipeline DAI 1 +PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, + 3, 0, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000, + SCHEDULE_TIME_DOMAIN_DMA, + PIPELINE_PLAYBACK_SCHED_COMP_1) + +# PCM Playback pipeline 4 on PCM 1 using max 2 channels of s32le. +# 10ms deadline on core 0 with priority 0 +# this is connected to pipeline DAI 1 +PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, + 4, 1, 2, s32le, + 10000, 0, 0, + 48000, 48000, 48000, + SCHEDULE_TIME_DOMAIN_DMA, + PIPELINE_PLAYBACK_SCHED_COMP_1) # Connect pipelines together -SectionGraph."pipe-cht-max98090" { +SectionGraph."PIPE_NAME" { index "0" lines [ - # media 0 + # PCM pipeline 3 to DAI pipeline 1 dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_3) + # PCM pipeline 4 to DAI pipeline 1 + dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_4) + ] } # capture DAI is SSP2 using 2 periods # Buffers use s16le format, 1000us deadline on core 0 with priority 0 +# this is part of pipeline 2 DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 2, SSP2-Codec, + 2, SSP, SSP_NUM, SSP2-Codec, PIPELINE_SINK_2, 2, s16le, 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) -# PCM Low Latency -PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) + +# PCM definitions +PCM_DUPLEX_ADD(PCM, 0, PIPELINE_PCM_3, PIPELINE_PCM_2) +PCM_PLAYBACK_ADD(PCM Deep Buffer, 1, PIPELINE_PCM_4) # # BE configurations - overrides config in ACPI if present # -DAI_CONFIG(SSP, 2, 0, SSP2-Codec, +DAI_CONFIG(SSP, SSP_NUM, 0, SSP2-Codec, SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), SSP_CLOCK(bclk, 1920000, codec_slave), SSP_CLOCK(fsync, 48000, codec_slave),