mirror of https://github.com/thesofproject/sof.git
platform: amd: renoir: Add debug support for renoir
Add panic code to dump required info during firmware exceptions. This patch enables to dump the call stack, debug info and inform host driver for exceptions in firmware. Signed-off-by: balapati <balakishore.pati@amd.com>
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@ -38,6 +38,14 @@
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#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
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#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET
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static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
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{
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volatile uint32_t *ptr;
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ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset);
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*ptr = src;
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}
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#endif /* __PLATFORM_LIB_MAILBOX_H__ */
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#else
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@ -20,6 +20,7 @@
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#include <stddef.h>
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#include <stdint.h>
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#include <platform/fw_scratch_mem.h>
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#include <platform/chip_registers.h>
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struct ll_schedule_domain;
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struct timer;
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@ -62,10 +63,24 @@ struct timer;
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/* default dma trace channel */
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#define DMA_TRACE_CHANNEL 7
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/* debug offset */
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#define ACP_SOF_FW_STATUS 0
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/* Platform defined panic code */
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static inline void platform_panic(uint32_t p)
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{
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/* TODO */
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acp_sw_intr_trig_t sw_intr_trig;
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volatile acp_scratch_mem_config_t *pscratch_mem_cfg =
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(volatile acp_scratch_mem_config_t *)(PU_REGISTER_BASE + SCRATCH_REG_OFFSET);
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pscratch_mem_cfg->acp_dsp_msg_write = p;
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mailbox_sw_reg_write(ACP_SOF_FW_STATUS, p);
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/* Read the Software Interrupt controller register and update */
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sw_intr_trig = (acp_sw_intr_trig_t) io_reg_read(PU_REGISTER_BASE + ACP_SW_INTR_TRIG);
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/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
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sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
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/* Write the Software Interrupt trigger register */
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io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
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}
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/*
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