mirror of https://github.com/thesofproject/sof.git
GDB: Context switch for debugging.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
parent
db3d730913
commit
a334567bc5
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@ -657,8 +657,8 @@ AC_CONFIG_FILES([
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src/platform/intel/cavs/Makefile
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test/Makefile
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test/cmocka/Makefile
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src/include/sof/gdb/Makefile
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src/gdb/Makefile
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src/arch/xtensa/include/arch/gdb/Makefile
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src/arch/xtensa/gdb/Makefile
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])
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AC_REQUIRE_AUX_FILE([tap-driver.sh])
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AC_OUTPUT
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@ -8,5 +8,5 @@ SUBDIRS = ipc math audio arch include library host
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endif
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if BUILD_XTENSA
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SUBDIRS = include gdb init math audio platform tasks drivers ipc lib arch
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SUBDIRS = include init math audio platform tasks drivers ipc lib arch
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endif
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@ -99,7 +99,6 @@ sof_LDADD = \
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../../audio/libaudio.a \
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../../drivers/libdrivers.la \
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../../math/libsof_math.a \
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../../gdb/libgdb.a \
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-lgcc
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if BUILD_XTENSA_SMP
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@ -2,6 +2,7 @@ noinst_LIBRARIES = libgdb.a
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libgdb_a_SOURCES = \
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init.S
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debugexception.S
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libgdb_a_CFLAGS = \
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$(AM_CFLAGS) \
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@ -0,0 +1,244 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
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*
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* Debug context switch.
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*
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*/
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#include <arch/gdb/xtensa-defs.h>
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#define DENSITY_BREAK_INS_IDENT 0x40
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#define NEXT_INST_OFFSET 0x03
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#define PS_EXCM_EXCEPTION_MODE 0x10
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#define PS_EXCM_MODE_MASK (~PS_EXCM_EXCEPTION_MODE)
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#define DEBUG_GDB_MEM_LOC 0x9E008060
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/*
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Save special register designated by 'reg' into
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backup space calculated by offset 'loc * 4' from
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memory pointed by a3.
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*/
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.macro SAVE_ reg, loc
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rsr a1, \reg
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s32i a1, a3, \loc * 4
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.endm
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.macro SAVE reg
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SAVE_ \reg, \reg
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.endm
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/*
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Load special register designated by 'reg' from
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backup space calculated by offset 'loc * 4' from
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memory pointed by a3.
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*/
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.macro LOAD_ reg, loc
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l32i a1, a3, \loc * 4
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wsr a1, \reg
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.endm
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.macro LOAD reg
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LOAD_ \reg, \reg
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.endm
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.text
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/*
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Temporary stack for context switch
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TODO: move it to dedicated GDB_STACK section
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*/
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gdb_stack:
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.fill 0x1000 , 4 , 0
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gdb_stack_end:
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.global DebugExceptionEntry
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.align 4
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/*
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Backup important special registers plus
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all regular ones (whole register file).
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Change EXCM field of PS back to normal mode
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after an interrupt took place.
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*/
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DebugExceptionEntry:
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movi a2, aregs
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s32i a0, a2, 0
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s32i a1, a2, 4
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rsr a1, DEBUG_EXCSAVE
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s32i a1, a2, 8
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s32i a3, a2, 12
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movi a3, sregs
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SAVE LBEG
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SAVE LEND
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SAVE LCOUNT
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SAVE SAR
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SAVE WINDOWBASE
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SAVE WINDOWSTART
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rsr a1, DEBUG_PC
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l8ui a2, a1, 1
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movi a0, DENSITY_BREAK_INS_IDENT
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bne a2, a0, 1f
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addi a1, a1, NEXT_INST_OFFSET
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1:
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s32i a1, a3, DEBUG_PC * 4
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SAVE EXCSAVE_1
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SAVE_ DEBUG_PS, PS
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SAVE EXCCAUSE
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SAVE DEBUGCAUSE
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SAVE EXCVADDR
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/*
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(XCHAL_NUM_AREGS / 4 - 1) - A number which holds information on how many
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registers are left to backup. Divide by four since we backup registers
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in group of four. Minus one, since one group has already been saved.
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*/
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movi a1, XCHAL_NUM_AREGS / 4 - 1
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movi a2, aregs
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1:
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s32i a4, a2, 16
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s32i a5, a2, 20
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s32i a6, a2, 24
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s32i a7, a2, 28
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addi a6, a2, 16
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addi a5, a1, -1
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rotw 1
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bnez a1, 1b
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movi a1, 1
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wsr a1, windowstart
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movi a0, 0
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wsr a0, windowbase
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rsync
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/* Setup of stack frame with 20 bytes for extra save area */
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movi a0, 0
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movi a1, gdb_stack + STACK_SIZE - 20
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rsr a2, PS
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/* Set exception mode back to normal */
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movi a3, PS_EXCM_MODE_MASK
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and a2, a2, a3
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wsr a2, PS
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rsync
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movi a4, handle_exception
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callx4 a4
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/*
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Restore important special registers plus
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all regular ones (whole register file).
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Change EXCM field of PS back to exception mode
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and return from interrupt.
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*/
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DebugExceptionExit:
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movi a2, DebugExceptionEntry
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wsr a2, DEBUG_EXCSAVE
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rsr a4, PS
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movi a3, PS_EXCM_EXCEPTION_MODE
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or a4, a4, a3
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wsr a4, PS
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rsync
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movi a3, sregs
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LOAD LBEG
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LOAD LEND
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LOAD LCOUNT
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LOAD SAR
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LOAD WINDOWBASE
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rsync
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movi a3, sregs
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LOAD WINDOWSTART
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LOAD DEBUG_PC
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LOAD EXCSAVE_1
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LOAD EXCCAUSE
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LOAD EXCVADDR
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LOAD INTENABLE
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rsync
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movi a6, aregs
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movi a5, XCHAL_NUM_AREGS / 4 - 2
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1:
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l32i a0, a6, 0
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l32i a1, a6, 4
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l32i a2, a6, 8
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l32i a3, a6, 12
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beqz a5, 2f
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addi a10, a6, 16
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addi a9, a5, -1
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rotw 1
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j 1b
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2:
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l32i a4, a6, 16
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l32i a5, a6, 20
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l32i a7, a6, 28
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l32i a6, a6, 24
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rotw 2
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rfi XCHAL_DEBUGLEVEL
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/*
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Put some important interrupt related registers into memory window
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pointed by DEBUG_GDB_MEM_LOC
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*/
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.global debug_exception
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.align 4
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debug_exception:
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entry a1, 16
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movi a3, DEBUG_GDB_MEM_LOC
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l32i a4, a2, 0 //load 4 bytes of message ID from incoming argv
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rsr a4, EPC_1
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rsr a5, EPC_2
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rsr a6, EXCCAUSE
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rsr a7, DEPC
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rsr a8, DEBUG_PS
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s32i a4, a3, 0
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s32i a5, a3, 4
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s32i a6, a3, 8
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s32i a7, a3, 12
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s32i a8, a3, 16
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isync
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rsync
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retw
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.size debug_exception, . -debug_exception
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@ -31,7 +31,7 @@
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*
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*/
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#include <sof/gdb/xtensa-defs.h>
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#include <arch/gdb/xtensa-defs.h>
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.text
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.global initDebugException
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@ -28,7 +28,7 @@
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#ifdef SIMULATOR
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#include <xtensa/simcall.h>
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#endif
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#include <sof/gdb/xtensa-defs.h>
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#include <arch/gdb/xtensa-defs.h>
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#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
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@ -28,7 +28,7 @@
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#ifdef SIMULATOR
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#include <xtensa/simcall.h>
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#endif
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#include <sof/gdb/xtensa-defs.h>
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#include <arch/gdb/xtensa-defs.h>
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#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
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