GDB: Context switch for debugging.

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
Marcin Rajwa 2019-01-10 16:06:38 +01:00 committed by Liam Girdwood
parent db3d730913
commit a334567bc5
10 changed files with 251 additions and 7 deletions

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@ -657,8 +657,8 @@ AC_CONFIG_FILES([
src/platform/intel/cavs/Makefile
test/Makefile
test/cmocka/Makefile
src/include/sof/gdb/Makefile
src/gdb/Makefile
src/arch/xtensa/include/arch/gdb/Makefile
src/arch/xtensa/gdb/Makefile
])
AC_REQUIRE_AUX_FILE([tap-driver.sh])
AC_OUTPUT

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@ -8,5 +8,5 @@ SUBDIRS = ipc math audio arch include library host
endif
if BUILD_XTENSA
SUBDIRS = include gdb init math audio platform tasks drivers ipc lib arch
SUBDIRS = include init math audio platform tasks drivers ipc lib arch
endif

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@ -99,7 +99,6 @@ sof_LDADD = \
../../audio/libaudio.a \
../../drivers/libdrivers.la \
../../math/libsof_math.a \
../../gdb/libgdb.a \
-lgcc
if BUILD_XTENSA_SMP

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@ -2,6 +2,7 @@ noinst_LIBRARIES = libgdb.a
libgdb_a_SOURCES = \
init.S
debugexception.S
libgdb_a_CFLAGS = \
$(AM_CFLAGS) \

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@ -0,0 +1,244 @@
/*
* Copyright (c) 2018, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Intel Corporation nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
*
* Debug context switch.
*
*/
#include <arch/gdb/xtensa-defs.h>
#define DENSITY_BREAK_INS_IDENT 0x40
#define NEXT_INST_OFFSET 0x03
#define PS_EXCM_EXCEPTION_MODE 0x10
#define PS_EXCM_MODE_MASK (~PS_EXCM_EXCEPTION_MODE)
#define DEBUG_GDB_MEM_LOC 0x9E008060
/*
Save special register designated by 'reg' into
backup space calculated by offset 'loc * 4' from
memory pointed by a3.
*/
.macro SAVE_ reg, loc
rsr a1, \reg
s32i a1, a3, \loc * 4
.endm
.macro SAVE reg
SAVE_ \reg, \reg
.endm
/*
Load special register designated by 'reg' from
backup space calculated by offset 'loc * 4' from
memory pointed by a3.
*/
.macro LOAD_ reg, loc
l32i a1, a3, \loc * 4
wsr a1, \reg
.endm
.macro LOAD reg
LOAD_ \reg, \reg
.endm
.text
/*
Temporary stack for context switch
TODO: move it to dedicated GDB_STACK section
*/
gdb_stack:
.fill 0x1000 , 4 , 0
gdb_stack_end:
.global DebugExceptionEntry
.align 4
/*
Backup important special registers plus
all regular ones (whole register file).
Change EXCM field of PS back to normal mode
after an interrupt took place.
*/
DebugExceptionEntry:
movi a2, aregs
s32i a0, a2, 0
s32i a1, a2, 4
rsr a1, DEBUG_EXCSAVE
s32i a1, a2, 8
s32i a3, a2, 12
movi a3, sregs
SAVE LBEG
SAVE LEND
SAVE LCOUNT
SAVE SAR
SAVE WINDOWBASE
SAVE WINDOWSTART
rsr a1, DEBUG_PC
l8ui a2, a1, 1
movi a0, DENSITY_BREAK_INS_IDENT
bne a2, a0, 1f
addi a1, a1, NEXT_INST_OFFSET
1:
s32i a1, a3, DEBUG_PC * 4
SAVE EXCSAVE_1
SAVE_ DEBUG_PS, PS
SAVE EXCCAUSE
SAVE DEBUGCAUSE
SAVE EXCVADDR
/*
(XCHAL_NUM_AREGS / 4 - 1) - A number which holds information on how many
registers are left to backup. Divide by four since we backup registers
in group of four. Minus one, since one group has already been saved.
*/
movi a1, XCHAL_NUM_AREGS / 4 - 1
movi a2, aregs
1:
s32i a4, a2, 16
s32i a5, a2, 20
s32i a6, a2, 24
s32i a7, a2, 28
addi a6, a2, 16
addi a5, a1, -1
rotw 1
bnez a1, 1b
movi a1, 1
wsr a1, windowstart
movi a0, 0
wsr a0, windowbase
rsync
/* Setup of stack frame with 20 bytes for extra save area */
movi a0, 0
movi a1, gdb_stack + STACK_SIZE - 20
rsr a2, PS
/* Set exception mode back to normal */
movi a3, PS_EXCM_MODE_MASK
and a2, a2, a3
wsr a2, PS
rsync
movi a4, handle_exception
callx4 a4
/*
Restore important special registers plus
all regular ones (whole register file).
Change EXCM field of PS back to exception mode
and return from interrupt.
*/
DebugExceptionExit:
movi a2, DebugExceptionEntry
wsr a2, DEBUG_EXCSAVE
rsr a4, PS
movi a3, PS_EXCM_EXCEPTION_MODE
or a4, a4, a3
wsr a4, PS
rsync
movi a3, sregs
LOAD LBEG
LOAD LEND
LOAD LCOUNT
LOAD SAR
LOAD WINDOWBASE
rsync
movi a3, sregs
LOAD WINDOWSTART
LOAD DEBUG_PC
LOAD EXCSAVE_1
LOAD EXCCAUSE
LOAD EXCVADDR
LOAD INTENABLE
rsync
movi a6, aregs
movi a5, XCHAL_NUM_AREGS / 4 - 2
1:
l32i a0, a6, 0
l32i a1, a6, 4
l32i a2, a6, 8
l32i a3, a6, 12
beqz a5, 2f
addi a10, a6, 16
addi a9, a5, -1
rotw 1
j 1b
2:
l32i a4, a6, 16
l32i a5, a6, 20
l32i a7, a6, 28
l32i a6, a6, 24
rotw 2
rfi XCHAL_DEBUGLEVEL
/*
Put some important interrupt related registers into memory window
pointed by DEBUG_GDB_MEM_LOC
*/
.global debug_exception
.align 4
debug_exception:
entry a1, 16
movi a3, DEBUG_GDB_MEM_LOC
l32i a4, a2, 0 //load 4 bytes of message ID from incoming argv
rsr a4, EPC_1
rsr a5, EPC_2
rsr a6, EXCCAUSE
rsr a7, DEPC
rsr a8, DEBUG_PS
s32i a4, a3, 0
s32i a5, a3, 4
s32i a6, a3, 8
s32i a7, a3, 12
s32i a8, a3, 16
isync
rsync
retw
.size debug_exception, . -debug_exception

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@ -31,7 +31,7 @@
*
*/
#include <sof/gdb/xtensa-defs.h>
#include <arch/gdb/xtensa-defs.h>
.text
.global initDebugException

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@ -28,7 +28,7 @@
#ifdef SIMULATOR
#include <xtensa/simcall.h>
#endif
#include <sof/gdb/xtensa-defs.h>
#include <arch/gdb/xtensa-defs.h>
#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS

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@ -28,7 +28,7 @@
#ifdef SIMULATOR
#include <xtensa/simcall.h>
#endif
#include <sof/gdb/xtensa-defs.h>
#include <arch/gdb/xtensa-defs.h>
#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS