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platform: amd: enabling support for sound wire 

Enabling sound wire support for amd platform

Signed-off-by: maruthi machani <maruthi.machani@amd.corp-partner.google.com>
This commit is contained in:
maruthi machani 2023-11-06 14:54:42 +05:30 committed by Kai Vehmanen
parent 3858532c76
commit 9dad60d0d9
5 changed files with 167 additions and 0 deletions
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34
src/platform/amd/acp_6_3/include/platform/chip_offset_byte.h
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@ -44,8 +44,23 @@
/* Registers from ACP_AUDIO_BUFFERS block */
#define ACP_AUDIO_RX_RINGBUFADDR 0x1242000
#define ACP_AUDIO_RX_RINGBUFSIZE 0x1242004
#define ACP_AUDIO_RX_LINKPOSITIONCNTR 0x1242008
#define ACP_AUDIO_RX_FIFOADDR 0x124200C
#define ACP_AUDIO_RX_FIFOSIZE 0x1242010
#define ACP_AUDIO_RX_DMA_SIZE 0x1242014
#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH 0x1242018
#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW 0x124201C
#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE 0x1242020
#define ACP_AUDIO_TX_RINGBUFADDR 0x1242024
#define ACP_AUDIO_TX_RINGBUFSIZE 0x1242028
#define ACP_AUDIO_TX_LINKPOSITIONCNTR 0x124202C
#define ACP_AUDIO_TX_FIFOADDR 0x1242030
#define ACP_AUDIO_TX_FIFOSIZE 0x1242034
#define ACP_AUDIO_TX_DMA_SIZE 0x1242038
#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH 0x124203C
#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW 0x1242040
#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE 0x1242044
#define ACP_BT_RX_RINGBUFADDR 0x1242048
#define ACP_BT_RX_RINGBUFSIZE 0x124204C
@ -112,6 +127,20 @@
#define ACP_WOV_MISC_CTRL 0x1242C5C
#define ACP_WOV_CLK_CTRL 0x1242C60
#define ACP_SW_EN 0x1243000
#define ACP_SW_EN_STATUS 0x1243004
#define ACP_SW_AUDIO_TX_EN 0x1243010
#define ACP_SW_AUDIO_TX_EN_STATUS 0x1243014
#define ACP_SW_BT_TX_EN 0x1243050
#define ACP_SW_BT_TX_EN_STATUS 0x1243054
#define ACP_SW_HS_TX_EN 0x124306C
#define ACP_SW_HS_TX_EN_STATUS 0x1243070
#define ACP_SW_AUDIO_RX_EN 0x1243088
#define ACP_SW_AUDIO_RX_EN_STATUS 0x124308C
#define ACP_SW_BT_RX_EN 0x1243128
#define ACP_SW_BT_RX_EN_STATUS 0x124312C
#define ACP_SW_HS_RX_EN 0x1243144
#define ACP_SW_HS_RX_EN_STATUS 0x1243148
/* Registers from ACP_P1_AUDIO_BUFFERS block */
#define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00
#define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04
@ -162,6 +191,11 @@
#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0
#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4
#define ACP_P1_SW_EN 0x1243C00
#define ACP_P1_SW_BT_TX_EN 0x1243C50
#define ACP_P1_SW_BT_TX_EN_STATUS 0x1243C54
#define ACP_P1_SW_BT_RX_EN 0x1243D28
#define ACP_P1_SW_BT_RX_EN_STATUS 0x1243D2C
#define MP1_SMN_C2PMSG_69 0x58A14
#define MP1_SMN_C2PMSG_85 0x58A54
#define MP1_SMN_C2PMSG_93 0x58A74

98
src/platform/amd/acp_6_3/lib/dai.c
View File

@ -72,6 +72,97 @@ static struct dai hsdai[] = {
}
};
static struct dai swaudiodai[] = {
{
.index = DI_SDW0_ACP_SW_AUDIO_TX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = DAI_BASE_REM + SW0_AUDIO_TX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_AUDIO_TX_EN_CH,
}
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW0_ACP_SW_AUDIO_RX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = DAI_BASE_REM + SW0_AUDIO_RX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_AUDIO_RX_EN_CH,
},
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW0_ACP_SW_BT_TX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = DAI_BASE_REM + BT0_TX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_BT_TX_EN_CH,
}
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW0_ACP_SW_BT_RX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = DAI_BASE_REM + BT0_RX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_BT_RX_EN_CH,
},
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW0_ACP_SW_HS_TX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = DAI_BASE_REM + HS0_TX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_HS_TX_EN_CH,
}
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW0_ACP_SW_HS_RX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = DAI_BASE_REM + HS0_RX_FIFO_OFFST,
.handshake = SDW0_ACP_SW_HS_RX_EN_CH,
},
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW1_ACP_P1_SW_BT_TX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = DAI_BASE_REM + BT_TX_FIFO_OFFST,
.handshake = SDW1_ACP_P1_SW_BT_TX_EN_CH,
}
},
.drv = &acp_swaudiodai_driver,
},
{
.index = DI_SDW1_ACP_P1_SW_BT_RX,
.plat_data = {
.base = DAI_BASE_REM,
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = DAI_BASE_REM + BT_RX_FIFO_OFFST,
.handshake = SDW1_ACP_P1_SW_BT_RX_EN_CH,
},
},
.drv = &acp_swaudiodai_driver,
},
};
#ifdef ACP_SP_ENABLE
static struct dai spdai[] = {
{
@ -165,6 +256,11 @@ const struct dai_type_info dti[] = {
.num_dais = ARRAY_SIZE(btdai)
},
#endif
{
.type = SOF_DAI_AMD_SW_AUDIO,
.dai_array = swaudiodai,
.num_dais = ARRAY_SIZE(swaudiodai)
},
};
const struct dai_info lib_dai = {
@ -181,6 +277,8 @@ int dai_init(struct sof *sof)
k_spinlock_init(&acp_dmic_dai[i].lock);
for (i = 0; i < ARRAY_SIZE(hsdai); i++)
k_spinlock_init(&hsdai[i].lock);
for (i = 0; i < ARRAY_SIZE(swaudiodai); i++)
k_spinlock_init(&swaudiodai[i].lock);
#ifdef ACP_SP_ENABLE
for (i = 0; i < ARRAY_SIZE(spdai); i++)
k_spinlock_init(&spdai[i].lock);

16
src/platform/amd/acp_6_3/lib/dma.c
View File

@ -23,6 +23,7 @@ extern struct dma_ops acp_dai_bt_dma_ops;
extern struct dma_ops acp_dai_sp_dma_ops;
#endif
extern struct dma_ops acp_dai_hs_dma_ops;
extern struct dma_ops acp_dai_sw_audio_dma_ops;
SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = {
{
@ -52,6 +53,21 @@ SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = {
},
.ops = &acp_dai_hs_dma_ops,
},
{
.plat_data = {
.id = DMA_ID_DAI_SW_AUDIO,
.dir = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
.devs = DMA_DEV_SW,
.caps = DMA_CAP_SW,
.base = DMA0_BASE,
.chan_size = DMA0_SIZE,
.channels = 8,
.irq = IRQ_NUM_EXT_LEVEL5,
.irq_name = "irqsteer1",
},
.ops = &acp_dai_sw_audio_dma_ops,
},
{
.plat_data = {
.id = DMA_ID_DAI_DMIC,

18
src/platform/amd/common/include/platform/lib/dai.h
View File

@ -10,6 +10,24 @@
#ifndef __PLATFORM_LIB_DAI_H__
#define __PLATFORM_LIB_DAI_H__
#define SDW0_ACP_SW_HS_RX_EN_CH 0
#define SDW0_ACP_SW_HS_TX_EN_CH 1
#define SDW1_ACP_P1_SW_BT_RX_EN_CH 2
#define SDW1_ACP_P1_SW_BT_TX_EN_CH 3
#define SDW0_ACP_SW_AUDIO_RX_EN_CH 4
#define SDW0_ACP_SW_AUDIO_TX_EN_CH 5
#define SDW0_ACP_SW_BT_RX_EN_CH 6
#define SDW0_ACP_SW_BT_TX_EN_CH 7
#define SDW0_ACP_SW_BT_CH_OFFSET 4
#define DI_SDW0_ACP_SW_AUDIO_TX 0
#define DI_SDW0_ACP_SW_BT_TX 1
#define DI_SDW0_ACP_SW_HS_TX 2
#define DI_SDW0_ACP_SW_AUDIO_RX 3
#define DI_SDW0_ACP_SW_BT_RX 4
#define DI_SDW0_ACP_SW_HS_RX 5
#define DI_SDW1_ACP_P1_SW_BT_TX 65
#define DI_SDW1_ACP_P1_SW_BT_RX 68
#endif /* __PLATFORM_LIB_DAI_H__ */

1
src/platform/amd/common/include/platform/lib/dma.h
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@ -23,6 +23,7 @@
#define DMA_ID_DAI_HS 5
#define DMA_ID_DAI_SP_VIRTUAL 6
#define DMA_ID_DAI_HS_VIRTUAL 7
#define DMA_ID_DAI_SW_AUDIO 8
#define dma_chan_irq(dma, chan) dma_irq(dma)