mirror of https://github.com/thesofproject/sof.git
platform: amd: enabling support for sound wire
Enabling sound wire support for amd platform Signed-off-by: maruthi machani <maruthi.machani@amd.corp-partner.google.com>
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3858532c76
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@ -44,8 +44,23 @@
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/* Registers from ACP_AUDIO_BUFFERS block */
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#define ACP_AUDIO_RX_RINGBUFADDR 0x1242000
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#define ACP_AUDIO_RX_RINGBUFSIZE 0x1242004
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#define ACP_AUDIO_RX_LINKPOSITIONCNTR 0x1242008
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#define ACP_AUDIO_RX_FIFOADDR 0x124200C
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#define ACP_AUDIO_RX_FIFOSIZE 0x1242010
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#define ACP_AUDIO_RX_DMA_SIZE 0x1242014
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#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH 0x1242018
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#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW 0x124201C
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#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE 0x1242020
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#define ACP_AUDIO_TX_RINGBUFADDR 0x1242024
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#define ACP_AUDIO_TX_RINGBUFSIZE 0x1242028
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#define ACP_AUDIO_TX_LINKPOSITIONCNTR 0x124202C
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#define ACP_AUDIO_TX_FIFOADDR 0x1242030
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#define ACP_AUDIO_TX_FIFOSIZE 0x1242034
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#define ACP_AUDIO_TX_DMA_SIZE 0x1242038
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#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH 0x124203C
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#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW 0x1242040
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#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE 0x1242044
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#define ACP_BT_RX_RINGBUFADDR 0x1242048
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#define ACP_BT_RX_RINGBUFSIZE 0x124204C
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@ -112,6 +127,20 @@
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#define ACP_WOV_MISC_CTRL 0x1242C5C
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#define ACP_WOV_CLK_CTRL 0x1242C60
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#define ACP_SW_EN 0x1243000
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#define ACP_SW_EN_STATUS 0x1243004
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#define ACP_SW_AUDIO_TX_EN 0x1243010
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#define ACP_SW_AUDIO_TX_EN_STATUS 0x1243014
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#define ACP_SW_BT_TX_EN 0x1243050
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#define ACP_SW_BT_TX_EN_STATUS 0x1243054
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#define ACP_SW_HS_TX_EN 0x124306C
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#define ACP_SW_HS_TX_EN_STATUS 0x1243070
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#define ACP_SW_AUDIO_RX_EN 0x1243088
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#define ACP_SW_AUDIO_RX_EN_STATUS 0x124308C
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#define ACP_SW_BT_RX_EN 0x1243128
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#define ACP_SW_BT_RX_EN_STATUS 0x124312C
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#define ACP_SW_HS_RX_EN 0x1243144
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#define ACP_SW_HS_RX_EN_STATUS 0x1243148
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/* Registers from ACP_P1_AUDIO_BUFFERS block */
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#define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00
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#define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04
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@ -162,6 +191,11 @@
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#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0
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#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4
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#define ACP_P1_SW_EN 0x1243C00
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#define ACP_P1_SW_BT_TX_EN 0x1243C50
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#define ACP_P1_SW_BT_TX_EN_STATUS 0x1243C54
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#define ACP_P1_SW_BT_RX_EN 0x1243D28
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#define ACP_P1_SW_BT_RX_EN_STATUS 0x1243D2C
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#define MP1_SMN_C2PMSG_69 0x58A14
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#define MP1_SMN_C2PMSG_85 0x58A54
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#define MP1_SMN_C2PMSG_93 0x58A74
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@ -72,6 +72,97 @@ static struct dai hsdai[] = {
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}
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};
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static struct dai swaudiodai[] = {
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{
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.index = DI_SDW0_ACP_SW_AUDIO_TX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = DAI_BASE_REM + SW0_AUDIO_TX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_AUDIO_TX_EN_CH,
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}
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW0_ACP_SW_AUDIO_RX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = DAI_BASE_REM + SW0_AUDIO_RX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_AUDIO_RX_EN_CH,
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},
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW0_ACP_SW_BT_TX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = DAI_BASE_REM + BT0_TX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_BT_TX_EN_CH,
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}
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW0_ACP_SW_BT_RX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = DAI_BASE_REM + BT0_RX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_BT_RX_EN_CH,
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},
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW0_ACP_SW_HS_TX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = DAI_BASE_REM + HS0_TX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_HS_TX_EN_CH,
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}
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW0_ACP_SW_HS_RX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = DAI_BASE_REM + HS0_RX_FIFO_OFFST,
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.handshake = SDW0_ACP_SW_HS_RX_EN_CH,
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},
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW1_ACP_P1_SW_BT_TX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = DAI_BASE_REM + BT_TX_FIFO_OFFST,
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.handshake = SDW1_ACP_P1_SW_BT_TX_EN_CH,
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}
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},
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.drv = &acp_swaudiodai_driver,
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},
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{
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.index = DI_SDW1_ACP_P1_SW_BT_RX,
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.plat_data = {
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.base = DAI_BASE_REM,
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = DAI_BASE_REM + BT_RX_FIFO_OFFST,
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.handshake = SDW1_ACP_P1_SW_BT_RX_EN_CH,
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},
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},
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.drv = &acp_swaudiodai_driver,
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},
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};
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#ifdef ACP_SP_ENABLE
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static struct dai spdai[] = {
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{
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@ -165,6 +256,11 @@ const struct dai_type_info dti[] = {
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.num_dais = ARRAY_SIZE(btdai)
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},
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#endif
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{
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.type = SOF_DAI_AMD_SW_AUDIO,
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.dai_array = swaudiodai,
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.num_dais = ARRAY_SIZE(swaudiodai)
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},
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};
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const struct dai_info lib_dai = {
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@ -181,6 +277,8 @@ int dai_init(struct sof *sof)
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k_spinlock_init(&acp_dmic_dai[i].lock);
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for (i = 0; i < ARRAY_SIZE(hsdai); i++)
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k_spinlock_init(&hsdai[i].lock);
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for (i = 0; i < ARRAY_SIZE(swaudiodai); i++)
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k_spinlock_init(&swaudiodai[i].lock);
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#ifdef ACP_SP_ENABLE
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for (i = 0; i < ARRAY_SIZE(spdai); i++)
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k_spinlock_init(&spdai[i].lock);
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@ -23,6 +23,7 @@ extern struct dma_ops acp_dai_bt_dma_ops;
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extern struct dma_ops acp_dai_sp_dma_ops;
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#endif
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extern struct dma_ops acp_dai_hs_dma_ops;
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extern struct dma_ops acp_dai_sw_audio_dma_ops;
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SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = {
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{
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},
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.ops = &acp_dai_hs_dma_ops,
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},
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{
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.plat_data = {
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.id = DMA_ID_DAI_SW_AUDIO,
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.dir = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV,
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.devs = DMA_DEV_SW,
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.caps = DMA_CAP_SW,
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.base = DMA0_BASE,
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.chan_size = DMA0_SIZE,
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.channels = 8,
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.irq = IRQ_NUM_EXT_LEVEL5,
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.irq_name = "irqsteer1",
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},
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.ops = &acp_dai_sw_audio_dma_ops,
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},
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{
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.plat_data = {
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.id = DMA_ID_DAI_DMIC,
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@ -10,6 +10,24 @@
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#ifndef __PLATFORM_LIB_DAI_H__
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#define __PLATFORM_LIB_DAI_H__
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#define SDW0_ACP_SW_HS_RX_EN_CH 0
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#define SDW0_ACP_SW_HS_TX_EN_CH 1
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#define SDW1_ACP_P1_SW_BT_RX_EN_CH 2
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#define SDW1_ACP_P1_SW_BT_TX_EN_CH 3
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#define SDW0_ACP_SW_AUDIO_RX_EN_CH 4
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#define SDW0_ACP_SW_AUDIO_TX_EN_CH 5
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#define SDW0_ACP_SW_BT_RX_EN_CH 6
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#define SDW0_ACP_SW_BT_TX_EN_CH 7
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#define SDW0_ACP_SW_BT_CH_OFFSET 4
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#define DI_SDW0_ACP_SW_AUDIO_TX 0
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#define DI_SDW0_ACP_SW_BT_TX 1
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#define DI_SDW0_ACP_SW_HS_TX 2
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#define DI_SDW0_ACP_SW_AUDIO_RX 3
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#define DI_SDW0_ACP_SW_BT_RX 4
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#define DI_SDW0_ACP_SW_HS_RX 5
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#define DI_SDW1_ACP_P1_SW_BT_TX 65
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#define DI_SDW1_ACP_P1_SW_BT_RX 68
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#endif /* __PLATFORM_LIB_DAI_H__ */
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@ -23,6 +23,7 @@
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#define DMA_ID_DAI_HS 5
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#define DMA_ID_DAI_SP_VIRTUAL 6
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#define DMA_ID_DAI_HS_VIRTUAL 7
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#define DMA_ID_DAI_SW_AUDIO 8
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#define dma_chan_irq(dma, chan) dma_irq(dma)
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