MEMORY: Enabled LP SRAM for ICL platform.

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>

src/arch/xtensa/boot_loader.c

@@ -240,6 +240,35 @@ static uint32_t hp_sram_init(void)
 
 #endif
 
+#if defined(CONFIG_ICELAKE)
+static int32_t lp_sram_init(void)
+{
+	int status;
+	unsigned int timeout_counter, delay_count = 256;
+	timeout_counter = delay_count;
+
+	shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
+
+	/* query the power status of first part of LP memory */
+	/* to check whether it has been powered up. A few    */
+	/* cycles are needed for it to be powered up         */
+	status = io_reg_read(LSPGISTS);
+	while (status) {
+		if (!timeout_counter--) {
+			platform_panic(SOF_IPC_PANIC_MEM);
+			break;
+		}
+		status = io_reg_read(LSPGISTS);
+	}
+
+	/* add some extra delay before touch power register */
+	idelay(delay_count);
+	shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS);
+
+	return status;
+}
+#endif
+
 /* boot master core */
 void boot_master_core(void)
 {
@@ -256,6 +285,17 @@ void boot_master_core(void)
 		return;
 	}
 
+#if defined(CONFIG_ICELAKE)
+	/* init the LPSRAM */
+	platform_trace_point(TRACE_BOOT_LDR_LPSRAM);
+
+	result = lp_sram_init();
+	if (result < 0) {
+		platform_panic(SOF_IPC_PANIC_MEM);
+		return;
+	}
+#endif
+
 #if defined(CONFIG_BOOT_LOADER)
 	/* parse manifest and copy modules */
 	platform_trace_point(TRACE_BOOT_LDR_MANIFEST);

src/include/sof/trace.h

@@ -48,6 +48,7 @@
 #define TRACE_BOOT_LDR_ENTRY		0x100
 #define TRACE_BOOT_LDR_HPSRAM		0x110
 #define TRACE_BOOT_LDR_MANIFEST		0x120
+#define TRACE_BOOT_LDR_LPSRAM		0x130
 #define TRACE_BOOT_LDR_JUMP		0x150
 
 #define TRACE_BOOT_LDR_PARSE_MODULE	0x210

src/platform/icelake/boot_ldr.x.in

@@ -35,6 +35,9 @@ MEMORY
   wnd0 :
         org = HP_SRAM_WIN0_BASE,
         len = HP_SRAM_WIN0_SIZE
+  lpsram_mem :
+        org = LP_SRAM_BASE,
+        len = LP_SRAM_SIZE
 }
 
 PHDRS
@@ -46,6 +49,7 @@ PHDRS
   sof_bss_data_phdr PT_LOAD;
   sof_stack_phdr PT_LOAD;
   wnd0_phdr PT_LOAD;
+  lpsram_mem_phdr PT_LOAD;
 }
 
 /*  Default entry point:  */
@@ -233,4 +237,10 @@ SECTIONS
     KEEP (*(.xt.profile_files))
     KEEP (*(.gnu.linkonce.xt.profile_files.*))
   }
+  .lpsram(NOLOAD) : ALIGN(8)
+  {
+    _lpsram_start = ABSOLUTE(.);
+    KEEP (*(*.lpsram))
+    _lpsram_end = ABSOLUTE(.);
+  } >lpsram_mem :lpsram_mem_phdr
 }

src/platform/icelake/icelake.x.in

@@ -119,6 +119,9 @@ MEMORY
   static_log_entries_seg (!ari) :
         org = LOG_ENTRY_ELF_BASE,
         len = LOG_ENTRY_ELF_SIZE
+  lpsram_mem :
+        org = LP_SRAM_BASE,
+        len = LP_SRAM_SIZE
 }
 
 PHDRS
@@ -158,6 +161,7 @@ PHDRS
   wnd2_phdr PT_LOAD;
   wnd3_phdr PT_LOAD;
   static_log_entries_phdr PT_NOTE;
+  lpsram_mem_phdr PT_LOAD;
 }
 
 /*  Default entry point:  */
@@ -575,4 +579,12 @@ SECTIONS
   {
     KEEP (*(.fw_ready))
   } >sof_data :sof_data_phdr
+
+  .lpsram(NOLOAD) : ALIGN(8)
+  {
+    _lpsram_start = ABSOLUTE(.);
+    KEEP (*(*.lpsram))
+    _lpsram_end = ABSOLUTE(.);
+  } >lpsram_mem :lpsram_mem_phdr
+
 }

src/platform/icelake/include/platform/memory.h

@@ -214,7 +214,6 @@
 /* window 1 */
 #define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
 #define SRAM_INBOX_SIZE		0x2000
-
 /* window 2 */
 #define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
 #define SRAM_DEBUG_SIZE		0x800
@@ -350,7 +349,7 @@
 
 /* LP SRAM */
 #define LP_SRAM_BASE		0xBE800000
-#define LP_SRAM_SIZE		0x00020000
+#define LP_SRAM_SIZE		0x00010000
 
 /* Heap section sizes for module pool */
 #define HEAP_RT_LP_COUNT8			0