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Topology: Rename pipe-src-playback.m4 macro 

This patch renames the macro to pipe-src-volume-playback.m4 for
consistency with other audio processing plus volume
pipelines. The topologies those use it are modified for the new
file name.

A new macro for testbench usage called pipe-src-playback.m4 is
added. It is plain SRC component pipeline without volume. The
volume component in the pipeline caused difficulties with test.
The script tools/test/topology/tplg-build.sh will use the
pipeline to create test topology for SRC component.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This commit is contained in:
Seppo Ingalsuo 2019-05-10 18:31:39 +03:00 committed by Tomasz Lauda
parent 31e67a227c
commit 992aa661ab
5 changed files with 106 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tools/topology/sof-apl-src-pcm512x.m4
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@ -32,7 +32,7 @@ dnl frames, deadline, priority, core)
# Playback pipeline 1 on PCM 0 using max 2 channels of s24le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-src-playback.m4,
PIPELINE_PCM_ADD(sof/pipe-src-volume-playback.m4,
1, 0, 2, s24le,
48, 1000, 0, 0)

2
tools/topology/sof-cml-rt5682-max98357a.m4
View File

@ -21,7 +21,7 @@ dnl frames, deadline, priority, core)
# Low Latency playback pipeline 7 on PCM 5 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-src-playback.m4,
PIPELINE_PCM_ADD(sof/pipe-src-volume-playback.m4,
7, 5, 2, s32le,
48, 1000, 0, 0)

2
tools/topology/sof-cml-src-rt5682.m4
View File

@ -37,7 +37,7 @@ dnl frames, deadline, priority, core)
# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-src-playback.m4,
PIPELINE_PCM_ADD(sof/pipe-src-volume-playback.m4,
1, 0, 2, s24le,
48, 1000, 0, 0)

41
tools/topology/sof/pipe-src-playback.m4
View File

@ -2,29 +2,19 @@
#
# Pipeline Endpoints for connection are :-
#
# host PCM_P --> SRC --> sink DAI0
# host PCM_P --> B0 --> SRC --> B1 --> sink DAI0
# Include topology builder
include(`utils.m4')
include(`src.m4')
include(`buffer.m4')
include(`pcm.m4')
include(`pga.m4')
include(`src.m4')
include(`dai.m4')
include(`mixercontrol.m4')
include(`pipeline.m4')
#
# Controls
#
# Volume Mixer control with max value of 32
C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID,
CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
CONTROLMIXER_MAX(, 32),
false,
CONTROLMIXER_TLV(TLV 32 steps from -64dB to 0dB for 2dB, vtlv_m64s2),
Channel register and shift for Front Left/Right,
LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
#
# Components and Buffers
@ -45,48 +35,29 @@ W_DATA(media_src_conf, media_src_tokens)
# "SRC" has 3 source and 3 sink periods
W_SRC(0, PIPELINE_FORMAT, 3, 3, media_src_conf)
#
# Volume Configuration
#
W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens,
LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"'
` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"'))
W_DATA(playback_pga_conf, playback_pga_tokens)
# "Volume" has 2 source and 2 sink periods
W_PGA(0, PIPELINE_FORMAT, 2, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume"))
# Playback Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_HOST_MEM_CAP)
W_BUFFER(1, COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_HOST_MEM_CAP)
W_BUFFER(2, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_DAI_MEM_CAP)
#
# Pipeline Graph
#
# host PCM_P --> B0 --> SRC 0 --> B1 Volume 0 --> B2 --> sink DAI0
# host PCM_P --> B0 --> SRC 0 --> B1 --> sink DAI0
P_GRAPH(pipe-pass-src-playback-PIPELINE_ID, PIPELINE_ID,
LIST(` ',
`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
`dapm(N_SRC(0), N_BUFFER(0))',
`dapm(N_BUFFER(1), N_SRC(0))',
`dapm(N_PGA(0), N_BUFFER(1))',
`dapm(N_BUFFER(2), N_PGA(0))'))
`dapm(N_BUFFER(1), N_SRC(0))'))
#
# Pipeline Source and Sinks
#
indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(1))
indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), SRC Playback PCM_ID)
#

97
tools/topology/sof/pipe-src-volume-playback.m4 Normal file
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@ -0,0 +1,97 @@
# Low Latency Passthrough with volume Pipeline and PCM
#
# Pipeline Endpoints for connection are :-
#
# host PCM_P --> SRC --> sink DAI0
# Include topology builder
include(`utils.m4')
include(`src.m4')
include(`buffer.m4')
include(`pcm.m4')
include(`pga.m4')
include(`dai.m4')
include(`mixercontrol.m4')
include(`pipeline.m4')
#
# Controls
#
# Volume Mixer control with max value of 32
C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID,
CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
CONTROLMIXER_MAX(, 32),
false,
CONTROLMIXER_TLV(TLV 32 steps from -64dB to 0dB for 2dB, vtlv_m64s2),
Channel register and shift for Front Left/Right,
LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
#
# Components and Buffers
#
# Host "SRC Playback" PCM
# with 3 sink and 0 source periods
W_PCM_PLAYBACK(PCM_ID, SRC Playback, 3, 0)
#
# SRC Configuration
#
W_VENDORTUPLES(media_src_tokens, sof_src_tokens, LIST(` ', `SOF_TKN_SRC_RATE_OUT "48000"'))
W_DATA(media_src_conf, media_src_tokens)
# "SRC" has 3 source and 3 sink periods
W_SRC(0, PIPELINE_FORMAT, 3, 3, media_src_conf)
#
# Volume Configuration
#
W_VENDORTUPLES(playback_pga_tokens, sof_volume_tokens,
LIST(` ', `SOF_TKN_VOLUME_RAMP_STEP_TYPE "0"'
` ', `SOF_TKN_VOLUME_RAMP_STEP_MS "250"'))
W_DATA(playback_pga_conf, playback_pga_tokens)
# "Volume" has 2 source and 2 sink periods
W_PGA(0, PIPELINE_FORMAT, 2, 2, playback_pga_conf, LIST(` ', "PIPELINE_ID Master Playback Volume"))
# Playback Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_HOST_MEM_CAP)
W_BUFFER(1, COMP_BUFFER_SIZE(3,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_HOST_MEM_CAP)
W_BUFFER(2, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_DAI_MEM_CAP)
#
# Pipeline Graph
#
# host PCM_P --> B0 --> SRC 0 --> B1 Volume 0 --> B2 --> sink DAI0
P_GRAPH(pipe-pass-src-playback-PIPELINE_ID, PIPELINE_ID,
LIST(` ',
`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
`dapm(N_SRC(0), N_BUFFER(0))',
`dapm(N_BUFFER(1), N_SRC(0))',
`dapm(N_PGA(0), N_BUFFER(1))',
`dapm(N_BUFFER(2), N_PGA(0))'))
#
# Pipeline Source and Sinks
#
indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), SRC Playback PCM_ID)
#
# PCM Configuration
#
PCM_CAPABILITIES(SRC Playback PCM_ID, `S32_LE,S24_LE,S16_LE', 8000, 192000, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)