mirror of https://github.com/thesofproject/sof.git
toolschain: update header files to support newer toolschain
This patch updates XTENSA toolschain from version RG-2017.7 to RI-2020.5. Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
Marcin Rajwa
Liam Girdwood
parent
6c17eba7e2
commit
94db5c7b2f
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@ -1,5 +1,6 @@
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/*
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* xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
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* xtensa/coreasm.h -- assembler-specific definitions that depend on
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* CORE configuration.
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*
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* Source for configuration-independent binaries (which link in a
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* configuration-specific HAL library) must NEVER include this file.
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@ -13,10 +14,8 @@
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* here until we have a proper configuration-independent header file.
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*/
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/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/coreasm.h#1 $ */
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/*
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* Copyright (c) 2000-2014 Tensilica Inc.
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* Copyright (c) 2000-2018 Cadence Design Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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@ -52,6 +51,7 @@
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#include <xtensa/config/core.h>
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#include <xtensa/config/specreg.h>
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#include <xtensa/config/system.h>
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#include <xtensa/xtensa-versions.h>
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/*
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* Assembly-language specific definitions (assembly macros, etc.).
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@ -97,18 +97,23 @@
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addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
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//srli \as, \as, 16 // check upper half (shift right 16 bits)
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extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
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1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
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1:
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bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
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addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
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srli \as, \as, 8 // shift right to check upper 8 bits
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1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
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1:
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bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
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addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
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srli \as, \as, 4 // shift right 4 bits to check upper half
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1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
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1:
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bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
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addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
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srli \as, \as, 2 // shift right 2 bits to check upper half
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1: bltui \as, 0x2, 1f // is it the lsbit?
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1:
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bltui \as, 0x2, 1f // is it the lsbit?
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addi \at, \at, 2 // no, increment result to upper bit (of 2)
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2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
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2:
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addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
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//srli \as, \as, 1
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1: // done! \at contains index of msbit set (or -1 if none set)
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.if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
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@ -294,12 +299,12 @@
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* crsil -- conditional RSIL (read/set interrupt level)
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*
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* Executes the RSIL instruction if it exists, else just reads PS.
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* The RSIL instruction does not exist in the new exception architecture
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* if the interrupt option is not selected.
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* The RSIL instruction does not exist in XEA2 if the interrupt
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* option is not selected.
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*/
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.macro crsil ar, newlevel
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#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
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#if XCHAL_HAVE_INTERRUPTS
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rsil \ar, \newlevel
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#else
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rsr.ps \ar
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@ -460,9 +465,11 @@
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bbsi.l a0, 30, 2f // branch if called with call12
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call8 .L__wdwspill_assist16 // called with call8, only need another 8
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retw
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1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
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1:
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call12 .L__wdwspill_assist16 // called with call4, only need another 12
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retw
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2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
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2:
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call4 .L__wdwspill_assist16 // called with call12, only need another 4
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retw
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# elif XCHAL_NUM_AREGS == 64
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entry sp, 48
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@ -470,9 +477,11 @@
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bbsi.l a0, 30, 2f // branch if called with call12
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call4 .L__wdwspill_assist52 // called with call8, only need a call4
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retw
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1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
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1:
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call8 .L__wdwspill_assist52 // called with call4, only need a call8
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retw
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2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
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2:
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call12 .L__wdwspill_assist40 // called with call12, can skip a call12
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retw
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# elif XCHAL_NUM_AREGS == 16
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entry sp, 16
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@ -480,8 +489,10 @@
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bbsi.l a0, 30, 2f // branch if called with call12
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movi a7, 0 // called with call8
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retw
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1: movi a11, 0 // called with call4
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2: retw // if called with call12, everything already spilled
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1:
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movi a11, 0 // called with call4
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2:
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retw // if called with call12, everything already spilled
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// movi a15, 0 // trick to spill all but the direct caller
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// j 1f
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@ -898,6 +909,9 @@
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*/
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.macro abi_entry_size locsize=0, callsize=0
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#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
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# if XCHAL_HAVE_XEA3
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.set .callsz, 32 /* call8 only */
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# else
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.ifeq \callsize
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.set .callsz, 16
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.else
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@ -915,6 +929,7 @@
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.endif
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.endif
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.endif
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# endif
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.set .locsz, .callsz + ((\locsize + 15) & -16)
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#else
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.set .callsz, \callsize
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@ -1018,6 +1033,16 @@
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#endif
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.endm
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#if XCHAL_HAVE_XEA3 && XCHAL_HW_MIN_VERSION == XTENSA_HWVERSION_RH_2016_0
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.macro halt imm=0
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.Lhalt\@: j .Lhalt\@
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.endm
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.macro halt.n
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halt 0
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.endm
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#endif
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/*
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* These macros are internal, subject to change, and should not be used in
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* any new code.
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@ -1055,5 +1080,122 @@
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# endif
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#endif
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/*
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* Macros to support virtual ops.
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*/
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#include <xtensa/tie/xt_virtualops.h>
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#ifndef XT_ADD_A
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.macro add.a a,b,c ; add \a, \b, \c ; .endm
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#endif
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#ifndef XT_ADDI_A
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.macro addi.a a,b,c ; addi \a, \b, \c ; .endm
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#endif
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#ifndef XT_ADDMI_A
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.macro addmi.a a,b,c ; addmi \a, \b, \c ; .endm
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#endif
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#ifndef XT_ADDX2_A
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.macro addx2.a a,b,c ; addx2 \a, \b, \c ; .endm
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#endif
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#ifndef XT_ADDX4_A
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.macro addx4.a a,b,c ; addx4 \a, \b, \c ; .endm
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#endif
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#ifndef XT_ADDX8_A
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.macro addx8.a a,b,c ; addx8 \a, \b, \c ; .endm
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#endif
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#ifndef XT_MOV_A
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.macro mov.a a,b ; mov \a, \b ; .endm
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#endif
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#ifndef XT_SUB_A
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.macro sub.a a,b,c ; sub \a, \b, \c ; .endm
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#endif
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/* Places the core-id in the requested AR register.*/
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.macro xt_core_id ar
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#if XCHAL_HAVE_PRID
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#if PRID_ID_BITS
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rsr.prid \ar
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extui \ar, \ar, PRID_ID_SHIFT, PRID_ID_BITS
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#else
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movi \ar, 0
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#endif
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#else
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movi \ar, 0
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#endif
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.endm
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.macro clr_dcache scratch1, scratch2, scratch3
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#if defined(XCHAL_DCACHE_SIZE) && (XCHAL_DCACHE_SIZE > 0)
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movi \scratch3, 0
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movi \scratch1, 0
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movi \scratch2, XCHAL_DCACHE_SIZE
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1:
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sdct \scratch3, \scratch1
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addi \scratch1, \scratch1, XCHAL_DCACHE_LINESIZE * (1 << XCHAL_DCACHE_LINES_PER_TAG_LOG2)
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bne \scratch1, \scratch2, 1b
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movi \scratch1, 0
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2:
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sdcw \scratch3, \scratch1
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addi \scratch1, \scratch1, 4
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bne \scratch1, \scratch2, 2b
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#endif
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.endm
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.macro clr_icache scratch1, scratch2, scratch3
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#if defined(XCHAL_ICACHE_SIZE) && (XCHAL_ICACHE_SIZE > 0)
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movi \scratch3, 0
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movi \scratch1, 0
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movi \scratch2, XCHAL_ICACHE_SIZE
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1:
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sict \scratch3, \scratch1
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addi \scratch1, \scratch1, XCHAL_ICACHE_LINESIZE
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bne \scratch1, \scratch2, 1b
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movi \scratch1, 0
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2:
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sicw \scratch3, \scratch1
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addi \scratch1, \scratch1, 4
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bne \scratch1, \scratch2, 2b
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#endif
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.endm
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.macro clr_localmem base_addr, bytes, scratch1, scratch2, scratch3
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movi \scratch1, \base_addr
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movi \scratch2, \base_addr + \bytes
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movi \scratch3, 0
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1:
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s32i \scratch3, \scratch1, 0
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addi \scratch1, \scratch1, 4
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bne \scratch1, \scratch2, 1b
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.endm
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.macro clr_all_localmems scratch1, scratch2, scratch3
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#if defined(XCHAL_INSTRAM0_SIZE) && (XCHAL_INSTRAM0_SIZE > 0)
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clr_localmem XCHAL_INSTRAM0_VADDR, XCHAL_INSTRAM0_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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#if defined(XCHAL_INSTRAM1_SIZE) && (XCHAL_INSTRAM1_SIZE > 0)
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clr_localmem XCHAL_INSTRAM1_VADDR, XCHAL_INSTRAM1_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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#if defined(XCHAL_DATARAM0_SIZE) && (XCHAL_DATARAM0_SIZE > 0)
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clr_localmem XCHAL_DATARAM0_VADDR, XCHAL_DATARAM0_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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#if defined(XCHAL_DATARAM1_SIZE) && (XCHAL_DATARAM1_SIZE > 0)
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clr_localmem XCHAL_DATARAM1_VADDR, XCHAL_DATARAM1_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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#if defined(XCHAL_URAM0_SIZE) && (XCHAL_URAM0_SIZE > 0)
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clr_localmem XCHAL_URAM0_VADDR, XCHAL_URAM0_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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#if defined(XCHAL_URAM1_SIZE) && (XCHAL_URAM1_SIZE > 0)
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clr_localmem XCHAL_URAM1_VADDR, XCHAL_URAM1_SIZE, \scratch1, \scratch2, \scratch3
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#endif
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.endm
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#endif /*XTENSA_COREASM_H*/
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@ -0,0 +1,37 @@
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// Customer ID=10631; Build=0x90af6; Copyright (c) 2017-2019 Cadence Design Systems, Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining
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// a copy of this software and associated documentation files (the
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// "Software"), to deal in the Software without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Software, and to
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// permit persons to whom the Software is furnished to do so, subject to
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// the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* Do not modify. This is automatically generated.*/
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/* parasoft-begin-suppress ALL "This file not MISRA checked." */
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#ifndef _XTENSA_xt_virtualops_h_HEADER
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#define _XTENSA_xt_virtualops_h_HEADER
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/* Header includes start */
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/* Header includes end */
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#endif /* !_XTENSA_xt_virtualops_h_HEADER */
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/* parasoft-end-suppress ALL "This file not MISRA checked." */
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