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topology: add adl.m4 

copy/pasted from tgl.m4, will need to differentiate later

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
Pierre-Louis Bossart 2021-03-29 15:13:44 -05:00 committed by Liam Girdwood
parent 8673f92feb
commit 8af787ae2b
1 changed files with 38 additions and 0 deletions
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38
tools/topology/platform/intel/adl.m4 Normal file
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#
# Tigerlake differentiation for pipelines and components
#
include(`memory.m4')
dnl Memory capabilities for different buffer types on Tigerlake
define(`PLATFORM_DAI_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_HOST_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_PASS_MEM_CAP',
MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))
# Low Latency PCM Configuration
W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "50000"'))
W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)
# Media PCM Configuration
W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "100000"'))
W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)
# Tone Signal Generator Configuration
W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "200000"'))
W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)
# DAI schedule Configuration - scheduled by IRQ
W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens,
LIST(` ', `SOF_TKN_SCHED_MIPS "5000"'))
W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)