mirror of https://github.com/thesofproject/sof.git
topology: align SoundWire topologies with the use of macros
No need for a dedicated topology just to deal with swapped links Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
Pierre-Louis Bossart
Liam Girdwood
parent
2ce64f914f
commit
8673f92feb
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@ -91,7 +91,7 @@ set(TPLGS
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-cml-rt711-rt1308-rt715\;-DPLATFORM=cml"
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-icl-rt711-rt1308-rt715\;-DPLATFORM=icl"
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-mono-rt715\;-DPLATFORM=tgl\;-DMONO"
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"sof-tgl-rt715-rt711-rt1308-hdmi\;sof-tgl-rt715-rt711-rt1308-mono\;-DPLATFORM=tgl"
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt715-rt711-rt1308-mono\;-DPLATFORM=tgl\;-DMONO\;-DMIC_LINK=0\;-DUAJ_LINK=1\;-DAMP_1_LINK=2"
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1308-rt715\;-DPLATFORM=tgl"
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"sof-icl-rt711-rt1308-rt715-hdmi\;sof-tgl-rt711-rt1316-rt714\;-DPLATFORM=tgl"
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"sof-cnl-rt5682-sdw2\;sof-cnl-rt5682-sdw2\;-DPLATFORM=cnl"
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@ -1,187 +0,0 @@
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#
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# Topology for Tigerlake with rt715 + rt711 + rt1308.
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`alh.m4')
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include(`muxdemux.m4')
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include(`hda.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Platform specific DSP configuration
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include(`platform/intel/'PLATFORM`.m4')
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DEBUG_START
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#
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# Define the pipelines
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#
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# PCM0 ---> volume ----> ALH 0x102 BE dailink 0
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# PCM1 <--- volume <---- ALH 0x103 BE dailink 1
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# PCM2 ---> volume ----> ALH 0x202 BE dailink 2
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# PCM4 <--- volume <---- ALH 0x2 BE dailink 4
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# PCM5 ---> volume ----> iDisp1
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# PCM6 ---> volume ----> iDisp2
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# PCM7 ---> volume ----> iDisp3
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl period, priority, core,
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dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
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dnl time_domain, sched_comp)
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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1, 0, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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2, 1, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 3 on PCM 2 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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3, 2, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency capture pipeline 5 on PCM 4 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-highpass-switch-capture.m4,
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5, 4, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 6 on PCM 5 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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6, 5, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 7 on PCM 6 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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7, 6, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 8 on PCM 7 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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8, 7, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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#
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# DAIs configuration
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#
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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# playback DAI is ALH(SDW1 PIN2) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, ALH, eval(1 * 256 + 2), SDW1-Playback,
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PIPELINE_SOURCE_1, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# capture DAI is ALH(SDW1 PIN3) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, ALH, eval(1 * 256 + 3), SDW1-Capture,
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PIPELINE_SINK_2, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is ALH(SDW2 PIN2) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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3, ALH, eval(2 * 256 + 2), SDW2-Playback,
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PIPELINE_SOURCE_3, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# capture DAI is ALH(SDW0 PIN2) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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5, ALH, eval(0 * 256 + 2), SDW0-Capture,
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PIPELINE_SINK_5, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp1 using 2 periods
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# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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6, HDA, 0, iDisp1,
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PIPELINE_SOURCE_6, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp2 using 2 periods
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# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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7, HDA, 1, iDisp2,
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PIPELINE_SOURCE_7, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp3 using 2 periods
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# # Buffers use s32le format, 1000us deadline on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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8, HDA, 2, iDisp3,
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PIPELINE_SOURCE_8, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# PCM Low Latency, id 0
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dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)
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PCM_PLAYBACK_ADD(Jack Out, 0, PIPELINE_PCM_1)
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PCM_CAPTURE_ADD(Jack In, 1, PIPELINE_PCM_2)
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PCM_PLAYBACK_ADD(Speaker, 2, PIPELINE_PCM_3)
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PCM_CAPTURE_ADD(Microphone, 4, PIPELINE_PCM_5)
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PCM_PLAYBACK_ADD(HDMI 1, 5, PIPELINE_PCM_6)
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PCM_PLAYBACK_ADD(HDMI 2, 6, PIPELINE_PCM_7)
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PCM_PLAYBACK_ADD(HDMI 3, 7, PIPELINE_PCM_8)
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#
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# BE configurations - overrides config in ACPI if present
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#
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#ALH dai index = ((link_id << 8) | PDI id)
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#ALH SDW1 Pin2 (ID: 0)
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DAI_CONFIG(ALH, eval(1 * 256 + 2), 0, SDW1-Playback,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(1 * 256 + 2), 48000, 2)))
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#ALH SDW1 Pin3 (ID: 1)
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DAI_CONFIG(ALH, eval(1 * 256 + 3), 1, SDW1-Capture,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(1 * 256 + 3), 48000, 2)))
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#ALH SDW2 Pin2 (ID: 2)
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DAI_CONFIG(ALH, eval(2 * 256 + 2), 2, SDW2-Playback,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(2 * 256 + 2), 48000, 2)))
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#ALH SDW0 Pin2 (ID: 4)
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DAI_CONFIG(ALH, eval(0 * 256 + 2), 4, SDW0-Capture,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, eval(0 * 256 + 2), 48000, 2)))
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# 3 HDMI/DP outputs (ID: 5,6,7)
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DAI_CONFIG(HDA, 0, 5, iDisp1,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2)))
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DAI_CONFIG(HDA, 1, 6, iDisp2,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2)))
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DAI_CONFIG(HDA, 2, 7, iDisp3,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2)))
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DEBUG_END
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