mirror of https://github.com/thesofproject/sof.git
Merge pull request #363 from jajanusz/apl-cleanup-merge-del-platform-c
apl: remove duplicated platform.c file
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84e15e721a
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/*
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* Copyright (c) 2017, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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* Keyon Jie <yang.jie@linux.intel.com>
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*/
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#include <platform/memory.h>
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#include <platform/mailbox.h>
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#include <platform/shim.h>
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#include <platform/dma.h>
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#include <platform/clk.h>
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#include <platform/timer.h>
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#include <platform/interrupt.h>
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#include <uapi/ipc.h>
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#include <sof/mailbox.h>
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#include <sof/dai.h>
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#include <sof/dma.h>
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#include <sof/sof.h>
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#include <sof/agent.h>
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#include <sof/work.h>
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#include <sof/clock.h>
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#include <sof/ipc.h>
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#include <sof/io.h>
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#include <sof/trace.h>
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#include <sof/audio/component.h>
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#include <string.h>
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#include <version.h>
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static const struct sof_ipc_fw_ready ready = {
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.hdr = {
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.cmd = SOF_IPC_FW_READY,
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.size = sizeof(struct sof_ipc_fw_ready),
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},
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.version = {
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.build = SOF_BUILD,
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.minor = SOF_MINOR,
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.major = SOF_MAJOR,
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.date = __DATE__,
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.time = __TIME__,
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.tag = SOF_TAG,
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},
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};
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#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
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#define NUM_APL_WINDOWS 7
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static const struct sof_ipc_window sram_window = {
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.ext_hdr = {
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.hdr.cmd = SOF_IPC_FW_READY,
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.hdr.size = sizeof(struct sof_ipc_window) +
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sizeof(struct sof_ipc_window_elem) * NUM_APL_WINDOWS,
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.type = SOF_IPC_EXT_WINDOW,
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},
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.num_windows = NUM_APL_WINDOWS,
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.window = {
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{
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.type = SOF_IPC_REGION_REGS,
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.id = 0, /* map to host window 0 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_SW_REG_SIZE,
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.offset = 0,
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},
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{
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.type = SOF_IPC_REGION_UPBOX,
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.id = 0, /* map to host window 0 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_DSPBOX_SIZE,
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.offset = MAILBOX_SW_REG_SIZE,
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},
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{
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.type = SOF_IPC_REGION_DOWNBOX,
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.id = 1, /* map to host window 1 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_HOSTBOX_SIZE,
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.offset = 0,
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},
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{
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.type = SOF_IPC_REGION_DEBUG,
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.id = 2, /* map to host window 2 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE,
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.offset = 0,
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},
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{
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.type = SOF_IPC_REGION_EXCEPTION,
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.id = 2, /* map to host window 2 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_EXCEPTION_SIZE,
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.offset = MAILBOX_EXCEPTION_OFFSET,
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},
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{
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.type = SOF_IPC_REGION_STREAM,
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.id = 2, /* map to host window 2 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_STREAM_SIZE,
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.offset = MAILBOX_STREAM_OFFSET,
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},
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{
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.type = SOF_IPC_REGION_TRACE,
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.id = 3, /* map to host window 3 */
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.flags = 0, // TODO: set later
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.size = MAILBOX_TRACE_SIZE,
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.offset = 0,
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},
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},
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};
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static struct work_queue_timesource platform_generic_queue = {
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.timer = {
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.id = TIMER3, /* external timer, XTAL 19.2M */
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.irq = IRQ_EXT_TSTAMP0_LVL2(0),
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},
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.clk = CLK_SSP,
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.notifier = NOTIFIER_ID_SSP_FREQ,
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.timer_set = platform_timer_set,
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.timer_clear = platform_timer_clear,
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.timer_get = platform_timer_get,
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};
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struct timer *platform_timer = &platform_generic_queue.timer;
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int platform_boot_complete(uint32_t boot_message)
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{
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mailbox_dspbox_write(0, &ready, sizeof(ready));
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mailbox_dspbox_write(sizeof(ready), &sram_window,
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sram_window.ext_hdr.hdr.size);
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/* boot now complete so we can relax the CPU */
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clock_set_freq(CLK_CPU, CLK_DEFAULT_CPU_HZ);
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/* tell host we are ready */
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ipc_write(IPC_DIPCIE, SRAM_WINDOW_HOST_OFFSET(0) >> 12);
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ipc_write(IPC_DIPCI, 0x80000000 | SOF_IPC_FW_READY);
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return 0;
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}
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static void platform_memory_windows_init(void)
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{
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/* window0, for fw status & outbox/uplink mbox */
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io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
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io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
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| DMWBA_READONLY | DMWBA_ENABLE);
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bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
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HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
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dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
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HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
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/* window1, for inbox/downlink mbox */
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io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
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io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
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| DMWBA_ENABLE);
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bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
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dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
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/* window2, for debug */
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io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
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io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
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| DMWBA_READONLY | DMWBA_ENABLE);
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bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
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dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
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/* window3, for trace */
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io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
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io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
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| DMWBA_READONLY | DMWBA_ENABLE);
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bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
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dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
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}
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/* init HW */
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static void platform_init_hw(void)
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{
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io_reg_write(SHIM_GENO, SHIM_GENO_SHIMOSEL |
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SHIM_GENO_MDIVOSEL | SHIM_GENO_DIOPTOSEL);
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io_reg_write(SHIM_DSPIOPO,
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SHIM_DSPIOPO_DMICOSEL | SHIM_DSPIOPO_I2SOSEL);
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io_reg_write(SHIM_LPGPDMAC(0),
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SHIM_LPGPDMAC_CHOSEL | SHIM_LPGPDMAC_CTLOSEL);
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io_reg_write(SHIM_LPGPDMAC(1),
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SHIM_LPGPDMAC_CHOSEL | SHIM_LPGPDMAC_CTLOSEL);
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}
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int platform_init(struct sof *sof)
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{
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struct dai *ssp;
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struct dai *dmic0;
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int i, ret;
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trace_point(TRACE_BOOT_PLATFORM_ENTRY);
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platform_init_hw();
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platform_interrupt_init();
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trace_point(TRACE_BOOT_PLATFORM_MBOX);
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platform_memory_windows_init();
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trace_point(TRACE_BOOT_PLATFORM_SHIM);
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/* init work queues and clocks */
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trace_point(TRACE_BOOT_PLATFORM_TIMER);
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platform_timer_start(&platform_generic_queue.timer);
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trace_point(TRACE_BOOT_PLATFORM_CLOCK);
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init_platform_clocks();
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trace_point(TRACE_BOOT_SYS_WORK);
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init_system_workq(&platform_generic_queue);
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/* init the system agent */
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sa_init(sof);
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/* Set CPU to default frequency for booting */
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trace_point(TRACE_BOOT_SYS_CPU_FREQ);
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clock_set_freq(CLK_CPU, CLK_MAX_CPU_HZ);
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/* set SSP clock to 19.2M */
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trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ);
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clock_set_freq(CLK_SSP, 19200000);
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/* initialise the host IPC mechanisms */
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trace_point(TRACE_BOOT_PLATFORM_IPC);
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ipc_init(sof);
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/* disable PM for boot */
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shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
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SHIM_CLKCTL_LPGPDMAFDCGB(0) |
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SHIM_CLKCTL_LPGPDMAFDCGB(1) |
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SHIM_CLKCTL_I2SFDCGB(3) |
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SHIM_CLKCTL_I2SFDCGB(2) |
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SHIM_CLKCTL_I2SFDCGB(1) |
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SHIM_CLKCTL_I2SFDCGB(0) |
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SHIM_CLKCTL_DMICFDCGB |
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SHIM_CLKCTL_I2SEFDCGB(1) |
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SHIM_CLKCTL_I2SEFDCGB(0) |
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SHIM_CLKCTL_TCPAPLLS |
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SHIM_CLKCTL_RAPLLC |
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SHIM_CLKCTL_RXOSCC |
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SHIM_CLKCTL_RFROSCC |
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SHIM_CLKCTL_TCPLCG(0) | SHIM_CLKCTL_TCPLCG(1));
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shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL));
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/* init DMACs */
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trace_point(TRACE_BOOT_PLATFORM_DMA);
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ret = dmac_init();
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if (ret < 0)
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return -ENODEV;
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/* init SSP ports */
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trace_point(TRACE_BOOT_PLATFORM_SSP);
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for (i = 0; i < PLATFORM_NUM_SSP; i++) {
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ssp = dai_get(SOF_DAI_INTEL_SSP, i);
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if (ssp == NULL)
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return -ENODEV;
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dai_probe(ssp);
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}
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/* Init DMIC. Note that the two PDM controllers and four microphones
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* supported max. those are available in platform are handled by dmic0.
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*/
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trace_point(TRACE_BOOT_PLATFORM_DMIC);
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dmic0 = dai_get(SOF_DAI_INTEL_DMIC, 0);
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if (!dmic0)
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return -ENODEV;
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dai_probe(dmic0);
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/* Initialize DMA for Trace*/
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dma_trace_init_complete(sof->dmat);
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return 0;
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}
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