topology: Added IGO_NR in sof-tgl-max98373-rt5682 topology.

This commit added IGO_NR component into sof-tgl-max98373-rt5682.m4 as DMIC capture PCM99 pipeline. Signed-off-by: fy.tsuo <fy.tsuo@intelli-go.com>
2021-04-09 11:13:53 +08:00 · 2021-04-09 11:13:53 +08:00 · 776977852a
parent 59d2318a4c
commit 776977852a
3 changed files with 42 additions and 17 deletions
--- a/tools/topology/platform/intel/intel-generic-dmic-kwd.m4
+++ b/tools/topology/platform/intel/intel-generic-dmic-kwd.m4
@ -42,7 +42,20 @@ ifdef(`DMIC_DAI_LINK_48k_NAME',`',define(DMIC_DAI_LINK_48k_NAME, `dmic01'))
 ifdef(`DMIC_DAI_LINK_16k_NAME',`',define(DMIC_DAI_LINK_16k_NAME, `dmic16k'))

 # DMICPROC is set by makefile, available type: passthrough/eq-iir-volume
-ifdef(`DMICPROC', , `define(DMICPROC, passthrough)')
+ifdef(`IGO',
+`define(DMICPROC, igonr)',
+`ifdef(`DMICPROC', , `define(DMICPROC, passthrough)')')
+
+# Prolong period to 16ms for igo_nr process
+ifdef(`IGO', `define(`INTEL_GENERIC_DMIC_KWD_PERIOD', 16000)', `define(`INTEL_GENERIC_DMIC_KWD_PERIOD', 1000)')
+
+# PCM is fix 16k for igo_nr
+ifdef(`IGO', `define(`PCM_RATE', 16000)', `define(`PCM_RATE', 48000)')
+
+# DMIC setting for igo_nr
+ifdef(`IGO', `define(`DMIC_CONFIG_CLK_MIN', 500000)', `define(`DMIC_CONFIG_CLK_MIN', 2400000)')
+ifdef(`IGO', `define(`DMIC_CONFIG_CLK_MAX', 1600000)', `define(`DMIC_CONFIG_CLK_MAX', 4800000)')
+ifdef(`IGO', `define(`DMIC_CONFIG_SAMPLE_RATE', 16000)', `define(`DMIC_CONFIG_SAMPLE_RATE', 48000)')

 #
 # Define the pipelines
@ -63,11 +76,12 @@ define(`PGA_NAME', Dmic0)

 PIPELINE_PCM_ADD(sof/pipe-`DMICPROC'-capture.m4,
        DMIC_PIPELINE_48k_ID, DMIC_PCM_48k_ID, CHANNELS, s32le,
-        1000, 0, 0, 48000, 48000, 48000)
+        INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 0, PCM_RATE, PCM_RATE, PCM_RATE)

 undefine(`PGA_NAME')
 undefine(`PIPELINE_FILTER1')
 undefine(`PIPELINE_FILTER2')
+undefine(`DMICPROC')

 #
 # KWD configuration
@ -96,7 +110,7 @@ dnl     deadline, priority, core, time_domain)
 DAI_ADD(sof/pipe-dai-capture.m4,
        DMIC_PIPELINE_48k_ID, DMIC, 0, DMIC_DAI_LINK_48k_NAME,
        concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le,
-        1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
+        INTEL_GENERIC_DMIC_KWD_PERIOD, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

 # capture DAI is DMIC 1 using 3 periods
 # Buffers use s32le format, with 320 frame per 20000us on core 0 with priority 0
@ -140,16 +154,16 @@ SectionGraph."pipe-sof-generic-keyword-detect" {
 dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config)
 ifelse(CHANNELS, 4,
 `DAI_CONFIG(DMIC, 0, DMIC_DAI_LINK_48k_ID, DMIC_DAI_LINK_48k_NAME,
-                DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000,
+                DMIC_CONFIG(1, DMIC_CONFIG_CLK_MIN, DMIC_CONFIG_CLK_MAX, 40, 60, DMIC_CONFIG_SAMPLE_RATE,
                DMIC_WORD_LENGTH(s32le), 200, DMIC, 0,
                PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1)))',
 `DAI_CONFIG(DMIC, 0, DMIC_DAI_LINK_48k_ID, DMIC_DAI_LINK_48k_NAME,
-                DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000,
+                DMIC_CONFIG(1, DMIC_CONFIG_CLK_MIN, DMIC_CONFIG_CLK_MAX, 40, 60, DMIC_CONFIG_SAMPLE_RATE,
                DMIC_WORD_LENGTH(s32le), 200, DMIC, 0,
                PDM_CONFIG(DMIC, 0, STEREO_PDM0)))')

 # dmic16k (ID: 2)
 DAI_CONFIG(DMIC, 1, DMIC_DAI_LINK_16k_ID, DMIC_DAI_LINK_16k_NAME,
-                DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000,
+                DMIC_CONFIG(1, DMIC_CONFIG_CLK_MIN, DMIC_CONFIG_CLK_MAX, 40, 60, 16000,
                DMIC_WORD_LENGTH(s32le), 400, DMIC, 1,
                PDM_CONFIG(DMIC, 1, STEREO_PDM0)))
--- a/tools/topology/sof-smart-amplifier.m4
+++ b/tools/topology/sof-smart-amplifier.m4
@ -88,6 +88,11 @@ ifdef(`SMART_PCM_ID',`',`fatal_error(note: Need to define PCM ID for sof-smart-a
 ifdef(`SMART_PCM_NAME',`',`fatal_error(note: Need to define Speaker PCM name for sof-smart-amplifier
 )')

+#The long process time (aprox. 8ms) and process length (16ms in 16k sample rate) of igo_nr starve
+#the scheduler and results in SMART_AMP underflow, ending up with smart_amp component reset and close.
+#So increase the buffer size of SMART_AMP is necessary.
+ifdef(`IGO', `define(`SMART_AMP_PERIOD', 16000)', `define(`SMART_AMP_PERIOD', 1000)')
+
 ifelse(SDW, `1',
 `
 #
@ -122,7 +127,7 @@ dnl     time_domain, sched_comp)
 # Set 1000us deadline on core 0 with priority 0
 PIPELINE_PCM_ADD(sof/pipe-smart-amplifier-playback.m4,
 	SMART_PB_PPL_ID, SMART_PCM_ID, SMART_PB_CH_NUM, s32le,
-	1000, 0, SMART_AMP_CORE,
+	SMART_AMP_PERIOD, 0, SMART_AMP_CORE,
 	48000, 48000, 48000)

 # Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.
@ -131,13 +136,13 @@ ifelse(SDW, `1',
 `
 PIPELINE_PCM_ADD(sof/pipe-amp-ref-capture.m4,
        SMART_REF_PPL_ID, eval(SMART_PCM_ID + 1), SMART_REF_CH_NUM, s32le,
-        1000, 0, 0,
+        SMART_AMP_PERIOD, 0, 0,
        48000, 48000, 48000)
 ',
 `
 PIPELINE_PCM_ADD(sof/pipe-amp-ref-capture.m4,
 	SMART_REF_PPL_ID, SMART_PCM_ID, SMART_REF_CH_NUM, s32le,
-	1000, 0, SMART_AMP_CORE,
+	SMART_AMP_PERIOD, 0, SMART_AMP_CORE,
 	48000, 48000, 48000)
 ')

@ -157,14 +162,14 @@ ifelse(SDW, `1',
 DAI_ADD(sof/pipe-dai-playback.m4,
        SMART_PB_PPL_ID, ALH, SMART_ALH_INDEX, SMART_ALH_PLAYBACK_NAME,
        SMART_PIPE_SOURCE, 2, s24le,
-        1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
+        SMART_AMP_PERIOD, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)

 # capture DAI is ALH(ALH_INDEX) using 2 periods
 # Buffers use s32le format, 1000us deadline on core 0 with priority 0
 DAI_ADD(sof/pipe-dai-capture.m4,
        SMART_REF_PPL_ID, ALH, eval(SMART_ALH_INDEX + 1), SMART_ALH_CAPTURE_NAME,
        SMART_PIPE_SINK, 2, s24le,
-        1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
+        SMART_AMP_PERIOD, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
 ',
 `
 # playback DAI is SSP(SPP_INDEX) using 2 periods
@ -172,14 +177,14 @@ DAI_ADD(sof/pipe-dai-capture.m4,
 DAI_ADD(sof/pipe-dai-playback.m4,
 	SMART_PB_PPL_ID, SSP, SMART_SSP_INDEX, SMART_SSP_NAME,
 	SMART_PIPE_SOURCE, 2, s32le,
-	1000, 0, SMART_AMP_CORE, SCHEDULE_TIME_DOMAIN_TIMER)
+	SMART_AMP_PERIOD, 0, SMART_AMP_CORE, SCHEDULE_TIME_DOMAIN_TIMER)

 # capture DAI is SSP(SSP_INDEX) using 2 periods
 # Buffers use s32le format, 1000us deadline on core 0 with priority 0
 DAI_ADD(sof/pipe-dai-capture.m4,
 	SMART_REF_PPL_ID, SSP, SMART_SSP_INDEX, SMART_SSP_NAME,
 	SMART_PIPE_SINK, 2, s32le,
-	1000, 0, SMART_AMP_CORE, SCHEDULE_TIME_DOMAIN_TIMER)
+	SMART_AMP_PERIOD, 0, SMART_AMP_CORE, SCHEDULE_TIME_DOMAIN_TIMER)
 ')

 # Connect demux to smart_amp
--- a/tools/topology/sof-tgl-max98373-rt5682.m4
+++ b/tools/topology/sof-tgl-max98373-rt5682.m4
@ -49,7 +49,13 @@ define(`SMART_SSP_NAME', concat(concat(`SSP', AMP_SSP),`-Codec'))
 #define BE dai_link ID
 define(`SMART_BE_ID', 7)
 #define SSP mclk
-define(`SSP_MCLK', 24576000)
+ifdef(`IGO', `define(`SSP_MCLK', 19200000)', `define(`SSP_MCLK', 24576000)')
+#define SSP bclk
+ifdef(`IGO', `define(`SSP_BCLK', 2400000)', `define(`SSP_BCLK', 3072000)')
+#define SSP_TDM_WIDTH
+ifdef(`IGO', `define(`SSP_TDM_WIDTH', 25)', `define(`SSP_TDM_WIDTH', 32)')
+#define SSP_CONFIG_DATA_VALID_BITS
+ifdef(`IGO', `define(`SSP_CONFIG_DATA_VALID_BITS', 24)', `define(`SSP_CONFIG_DATA_VALID_BITS', 32)')
 # Playback related
 define(`SMART_PB_PPL_ID', 1)
 define(`SMART_PB_CH_NUM', 2)
@ -230,10 +236,10 @@ dnl ssp1-maxmspk, ssp0-RTHeadset
 #SSP 0 (ID: 0)
 DAI_CONFIG(SSP, 0, 0, SSP0-Codec,
        SSP_CONFIG(I2S, SSP_CLOCK(mclk, SSP_MCLK, codec_mclk_in),
-                      SSP_CLOCK(bclk, 3072000, codec_slave),
+                      SSP_CLOCK(bclk, SSP_BCLK, codec_slave),
                      SSP_CLOCK(fsync, 48000, codec_slave),
-                      SSP_TDM(2, 32, 3, 3),
-                      SSP_CONFIG_DATA(SSP, 0, 32)))
+                      SSP_TDM(2, SSP_TDM_WIDTH, 3, 3),
+                      SSP_CONFIG_DATA(SSP, 0, SSP_CONFIG_DATA_VALID_BITS)))

 # 4 HDMI/DP outputs (ID: 3,4,5,6)
 DAI_CONFIG(HDA, 0, 3, iDisp1,