From 72a51a462fb833a6fa1978d0aad047c71c37f58b Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Thu, 20 May 2021 11:17:11 +0300 Subject: [PATCH] cavs: memory: fix panic on tplg load for zephyr on cavs20/25 The Zephyr linker scripts for cavs20/25 do not map sections on uncached RAM, so the memory accesses to uncached memory will fail. This shows up as a DSP panic while loading initial topology. Signed-off-by: Kai Vehmanen --- src/platform/intel/cavs/include/cavs/lib/memory.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/platform/intel/cavs/include/cavs/lib/memory.h b/src/platform/intel/cavs/include/cavs/lib/memory.h index e16a4cd02..dbdcb1948 100644 --- a/src/platform/intel/cavs/include/cavs/lib/memory.h +++ b/src/platform/intel/cavs/include/cavs/lib/memory.h @@ -87,7 +87,7 @@ struct sof; #define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_OFFSET SRAM_UNCACHED_ALIAS -#if !defined UNIT_TEST +#if !defined UNIT_TEST && (CAVS_VERSION <= CAVS_VERSION_1_8 || !defined __ZEPHYR__) #define uncache_to_cache(address) \ ((__typeof__(address))((uint32_t)(address) | SRAM_ALIAS_OFFSET)) #define cache_to_uncache(address) \