mirror of https://github.com/thesofproject/sof.git
hda-dma: validate channels and improve trace output
Validate user supplied data and improve trace output on any errors. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood
parent
7db073a354
commit
713ba7de81
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@ -50,10 +50,12 @@
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#include <arch/cache.h>
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#include <uapi/ipc/topology.h>
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#define trace_host(__e, ...) \
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trace_event(TRACE_CLASS_HOST, __e, ##__VA_ARGS__)
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#define tracev_host(__e) tracev_event(TRACE_CLASS_HOST, __e)
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#define trace_host_error(__e) trace_error(TRACE_CLASS_HOST, __e)
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#define trace_hddma(__e, ...) \
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trace_event(TRACE_CLASS_DMA, __e, ##__VA_ARGS__)
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#define tracev_hddma(__e, ...) \
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tracev_event(TRACE_CLASS_DMA, __e, ##__VA_ARGS__)
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#define trace_hddma_error(__e, ...) \
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trace_error(TRACE_CLASS_DMA, __e, ##__VA_ARGS__)
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/* Gateway Stream Registers */
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#define DGCS 0x00
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@ -157,25 +159,51 @@ static inline void hda_dma_inc_link_fp(struct dma *dma, uint32_t chan,
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static inline uint32_t hda_dma_get_data_size(struct dma *dma, uint32_t chan)
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{
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const uint32_t cs = host_dma_reg_read(dma, chan, DGCS);
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const uint32_t bs = host_dma_reg_read(dma, chan, DGBS);
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const uint32_t rp = host_dma_reg_read(dma, chan, DGBRP);
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const uint32_t wp = host_dma_reg_read(dma, chan, DGBWP);
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uint32_t cs;
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uint32_t bs;
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uint32_t rp;
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uint32_t wp;
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int32_t ds;
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if (chan >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, chan);
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return 0;
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}
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cs = host_dma_reg_read(dma, chan, DGCS);
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bs = host_dma_reg_read(dma, chan, DGBS);
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rp = host_dma_reg_read(dma, chan, DGBRP);
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wp = host_dma_reg_read(dma, chan, DGBWP);
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if (!(cs & DGCS_BNE))
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return 0; /* buffer is empty */
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ds = (int32_t)wp - (int32_t)rp;
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if (ds <= 0)
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if (ds <= 0) {
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ds += bs;
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if (ds < 0) {
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trace_hddma_error("hda-dmac: %d channel %d invalid data size ds 0x%x bs 0x%x",
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dma->plat_data.id, chan, ds, bs);
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return 0;
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}
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}
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return ds;
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}
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static inline uint32_t hda_dma_get_free_size(struct dma *dma, uint32_t chan)
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{
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const uint32_t bs = host_dma_reg_read(dma, chan, DGBS);
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uint32_t bs;
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if (chan >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, chan);
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return 0;
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}
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bs = host_dma_reg_read(dma, chan, DGBS);
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return bs - hda_dma_get_data_size(dma, chan);
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}
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@ -195,7 +223,7 @@ static int hda_dma_preload(struct dma *dma, struct hda_chan_data *chan)
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*/
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while (!(host_dma_reg_read(dma, chan->index, DGCS) & DGCS_BF) &&
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(chan->state & HDA_STATE_BF_WAIT))
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;
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; /* TODO: this should timeout and not wait forever */
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if (host_dma_reg_read(dma, chan->index, DGCS) & DGCS_BF) {
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chan->state &= ~(HDA_STATE_PRELOAD | HDA_STATE_BF_WAIT);
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@ -227,7 +255,8 @@ static int hda_dma_copy_ch(struct dma *dma, struct hda_chan_data *chan,
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uint32_t flags;
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uint32_t dgcs = 0;
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tracev_host("GwU");
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tracev_hddma("hda-dmac: %d channel %d copy 0x%x bytes",
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dma->plat_data.id, chan->index, bytes);
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/* clear link xruns */
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dgcs = host_dma_reg_read(dma, chan->index, DGCS);
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@ -275,9 +304,15 @@ static void hda_dma_init(struct dma *dma, int channel)
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struct dma_pdata *p = dma_get_drvdata(dma);
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uint32_t flags;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("hda-dma-init %p ch %d", (uintptr_t)dma, channel);
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trace_hddma("dmac %d channel %d init", dma->plat_data.id, channel);
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/* enable the channel */
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hda_update_bits(dma, channel, DGCS, DGCS_GEN | DGCS_FIFORDY,
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@ -317,6 +352,12 @@ static int hda_dma_copy(struct dma *dma, int channel, int bytes, uint32_t flags)
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struct dma_pdata *p = dma_get_drvdata(dma);
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struct hda_chan_data *chan = p->chan + channel;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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if (flags & DMA_COPY_PRELOAD)
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chan->state |= HDA_STATE_PRELOAD;
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@ -336,9 +377,15 @@ static int hda_dma_channel_get(struct dma *dma, int channel)
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struct dma_pdata *p = dma_get_drvdata(dma);
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uint32_t flags;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("Dgt");
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trace_hddma("hda-dmac: %d channel %d get", dma->plat_data.id, channel);
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/* use channel if it's free */
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if (p->chan[channel].status == COMP_STATE_INIT) {
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@ -353,7 +400,8 @@ static int hda_dma_channel_get(struct dma *dma, int channel)
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/* DMAC has no free channels */
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spin_unlock_irq(&dma->lock, flags);
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trace_host_error("eG0");
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trace_hddma_error("hda-dmac: %d no free channel %d", dma->plat_data.id,
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channel);
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return -ENODEV;
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}
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@ -362,6 +410,12 @@ static void hda_dma_channel_put_unlocked(struct dma *dma, int channel)
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{
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struct dma_pdata *p = dma_get_drvdata(dma);
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return;
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}
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/* set new state */
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p->chan[channel].status = COMP_STATE_INIT;
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p->chan[channel].state = 0;
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@ -392,18 +446,25 @@ static int hda_dma_start(struct dma *dma, int channel)
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uint32_t dgcs;
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int ret = 0;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("DEn");
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trace_hddma("hda-dmac: %d channel %d -> start", dma->plat_data.id,
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channel);
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/* is channel idle, disabled and ready ? */
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dgcs = host_dma_reg_read(dma, channel, DGCS);
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if (p->chan[channel].status != COMP_STATE_PREPARE ||
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(dgcs & DGCS_GEN)) {
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ret = -EBUSY;
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trace_host_error("eS0");
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trace_error_value(dgcs);
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trace_error_value(p->chan[channel].status);
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trace_hddma_error("hda-dmac: %d channel %d busy. dgcs 0x%x status %d",
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dma->plat_data.id, channel, dgcs,
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p->chan[channel].status);
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goto out;
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}
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@ -433,10 +494,16 @@ static int hda_dma_release(struct dma *dma, int channel)
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*/
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uint32_t flags;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("hda-dma-release dma-ptr: %p channel-number: %u",
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(uint32_t)dma, channel);
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trace_hddma("hda-dmac: %d channel %d -> release", dma->plat_data.id,
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channel);
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spin_unlock_irq(&dma->lock, flags);
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return 0;
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@ -447,9 +514,15 @@ static int hda_dma_pause(struct dma *dma, int channel)
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struct dma_pdata *p = dma_get_drvdata(dma);
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uint32_t flags;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("Dpa");
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trace_hddma("hda-dmac: %d channel %d -> pause", dma->plat_data.id, channel);
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if (p->chan[channel].status != COMP_STATE_ACTIVE)
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goto out;
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@ -467,9 +540,15 @@ static int hda_dma_stop(struct dma *dma, int channel)
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struct dma_pdata *p = dma_get_drvdata(dma);
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uint32_t flags;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("DDi");
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trace_hddma("hda-dmac: %d channel %d -> stop", dma->plat_data.id, channel);
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if (p->chan[channel].dma_ch_work.cb)
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work_cancel_default(&p->chan[channel].dma_ch_work);
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@ -488,6 +567,12 @@ static int hda_dma_status(struct dma *dma, int channel,
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{
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struct dma_pdata *p = dma_get_drvdata(dma);
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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status->state = p->chan[channel].status;
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status->r_pos = host_dma_reg_read(dma, channel, DGBRP);
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status->w_pos = host_dma_reg_read(dma, channel, DGBWP);
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@ -511,12 +596,19 @@ static int hda_dma_set_config(struct dma *dma, int channel,
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int i;
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int ret = 0;
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if (channel >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, channel);
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return -EINVAL;
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}
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spin_lock_irq(&dma->lock, flags);
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trace_host("Dsc");
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trace_hddma("hda-dmac: %d channel %d config", dma->plat_data.id, channel);
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if (!config->elem_array.count) {
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trace_host_error("eD1");
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trace_hddma_error("hda-dmac: %d channel %d no DMA descriptors",
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dma->plat_data.id, channel);
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ret = -EINVAL;
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goto out;
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}
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@ -537,14 +629,19 @@ static int hda_dma_set_config(struct dma *dma, int channel,
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/* make sure elem is continuous */
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if (buffer_addr && (buffer_addr + buffer_bytes) != addr) {
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trace_host_error("eD2");
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trace_hddma_error("hda-dmac: %d chan %d - non continuous elem",
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dma->plat_data.id, channel);
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trace_hddma_error(" addr 0x%x buffer 0x%x size 0x%x",
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addr, buffer_addr, buffer_bytes);
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ret = -EINVAL;
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goto out;
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}
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/* make sure period_bytes are constant */
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if (period_bytes && period_bytes != sg_elem->size) {
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trace_host_error("eD3");
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trace_hddma_error("hda-dmac: %d chan %d - period size not constant %d",
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dma->plat_data.id, channel,
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period_bytes);
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ret = -EINVAL;
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goto out;
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}
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@ -556,8 +653,11 @@ static int hda_dma_set_config(struct dma *dma, int channel,
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if (buffer_addr == 0)
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buffer_addr = addr;
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}
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/* buffer size must be multiple of hda dma burst size */
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if (buffer_bytes % PLATFORM_HDA_BUFFER_ALIGNMENT) {
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trace_hddma_error("hda-dmac: %d chan %d - buffer not DMA aligned 0x%x",
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dma->plat_data.id, channel, buffer_bytes);
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ret = -EINVAL;
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goto out;
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}
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@ -638,7 +738,7 @@ static int hda_dma_probe(struct dma *dma)
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int i;
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struct hda_chan_data *chan;
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trace_event(TRACE_CLASS_DMA, "hda-dma-probe %p id %d",
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trace_event(TRACE_CLASS_DMA, "dmac :%d probe",
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(uintptr_t)dma, dma->plat_data.id);
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if (dma_get_drvdata(dma))
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