Merge pull request #639 from mrajwa/gdb_support

GDB: Initial commit - added debug vector and init code.

configure.ac

@@ -83,6 +83,12 @@ if test "$have_roms" = "yes"; then
 	AC_DEFINE([CONFIG_ENABLE_ROMS], [1], [Enable building ROMs for QEMU])
 fi
 
+# check if we should enable GDB debugging
+AC_ARG_ENABLE(gdb_debug, [AS_HELP_STRING([--enable-gdb-debug],[gdb debug supported])], enable_gdb_debug=$enableval, have_roms=no)
+if test "$enable_gdb_debug" = "yes"; then
+	AC_DEFINE([CONFIG_GDB_DEBUG], [1], [Enable debugging with GDB])
+fi
+
 # check if we are building FW image or library
 AC_ARG_ENABLE(library, [AS_HELP_STRING([--enable-library],[build library])], have_library=$enableval, have_library=no)
 if test "$have_library" = "yes"; then
@@ -637,6 +643,8 @@ AC_CONFIG_FILES([
 	src/platform/intel/cavs/Makefile
 	test/Makefile
 	test/cmocka/Makefile
+	src/include/sof/gdb/Makefile
+	src/gdb/Makefile
 ])
 AC_REQUIRE_AUX_FILE([tap-driver.sh])
 AC_OUTPUT

src/Makefile.am

@@ -8,5 +8,5 @@ SUBDIRS = ipc math audio arch include library host
 endif
 
 if BUILD_XTENSA
-SUBDIRS = include init math audio platform tasks drivers ipc lib arch
+SUBDIRS = include gdb init math audio platform tasks drivers ipc lib arch
 endif

src/arch/xtensa/Makefile.am

@@ -99,6 +99,7 @@ sof_LDADD = \
 	../../audio/libaudio.a \
 	../../drivers/libdrivers.la \
 	../../math/libsof_math.a \
+	../../gdb/libgdb.a \
 	-lgcc
 
 if BUILD_XTENSA_SMP

src/arch/xtensa/smp/xtos/Makefile.am

@@ -126,6 +126,7 @@ libxtos_a_SOURCES = \
 	core-save.S \
 	core-shutoff.S \
 	double-vector.S \
+	debug-vector.S \
 	xea1/exc-alloca-handler.S \
 	xea1/exc-c-wrapper-handler.S \
 	xea2/exc-c-wrapper-handler.S \

src/arch/xtensa/smp/xtos/debug-vector.S

@@ -1,5 +1,5 @@
 // debug-vector.S  --  Debug Exception Vector
-// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/xtos/debug-vector.S#1 $
+// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/debug-vector.S#2 $
 
 // Copyright (c) 2003-2013 Tensilica Inc.
 //
@@ -24,7 +24,11 @@
 
 #include <xtensa/xtensa-versions.h>
 #include <xtensa/coreasm.h>
+#include <xtensa/config/specreg.h>
+#ifdef SIMULATOR
 #include <xtensa/simcall.h>
+#endif
+#include <sof/gdb/xtensa-defs.h>
 
 #if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
 
@@ -36,29 +40,33 @@
 	.global	_DebugExceptionVector
 _DebugExceptionVector:
 
-# if defined(SIMULATOR) || XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2	/* SIMCALL is NOP in hw? */
+	isync_erratum453
+#if ((defined(SIMULATOR) || \
+    (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2)) \
+    && !defined(CONFIG_GDB_DEBUG)) /* SIMCALL is NOP in hw? */
 	//  In the simulator (ISS), let the debugger (if any is attached)
 	//  handle the debug exception, else simply stop the simulation:
 	//
-	writesr	excsave XCHAL_DEBUGLEVEL a2	// save a2 where simulator expects it
+	simcall	// have ISS handle the debug exception
-	movi	a2, SYS_gdb_enter_sktloop
-	simcall					// have ISS handle the debug exception
 # endif
-# ifndef SIMULATOR
+# if (!defined(SIMULATOR) && !defined(CONFIG_GDB_DEBUG))
 	//  For hardware, this code does not handle debug exceptions.
 	//  To implement a target-side debug monitor, replace this
 	//  vector with a real one that uses target-specific facilities
 	//  to communicate with the debugger.
 	//  
 1:
-#  if XCHAL_HAVE_INTERRUPTS
+	// unexpected debug exception, loop in low-power mode
-	//waiti	XCHAL_DEBUGLEVEL // unexpected debug exception, loop in low-power mode
+	//waiti	XCHAL_DEBUGLEVEL
-#  endif
 	j	1b		// infinite loop - unexpected debug exception
-# endif /*!SIMULATOR*/
+# endif /*!SIMULATOR && !CONFIG_GDB_DEBUG*/
+
+#if defined(CONFIG_GDB_DEBUG)
+	xsr	a2, DEBUG_EXCSAVE
+	jx	a2
+#endif
 
 	.end	literal_prefix
 	.size	_DebugExceptionVector, . - _DebugExceptionVector
 
 #endif /* XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS */
-

src/arch/xtensa/up/xtos/Makefile.am

@@ -120,6 +120,7 @@ libxtos_a_SOURCES = \
 	core-save.S \
 	core-shutoff.S \
 	double-vector.S \
+	debug-vector.S \
 	exc-alloca-handler.S \
 	exc-c-wrapper-handler.S \
 	exc-return.S \

src/arch/xtensa/up/xtos/debug-vector.S

@@ -25,7 +25,10 @@
 #include <xtensa/xtensa-versions.h>
 #include <xtensa/coreasm.h>
 #include <xtensa/config/specreg.h>
+#ifdef SIMULATOR
 #include <xtensa/simcall.h>
+#endif
+#include <sof/gdb/xtensa-defs.h>
 
 #if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS
 
@@ -38,29 +41,32 @@
 _DebugExceptionVector:
 
 	isync_erratum453
-# if defined(SIMULATOR) || XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2	/* SIMCALL is NOP in hw? */
+#if ((defined(SIMULATOR) || \
+    (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2013_2)) \
+    && !defined(CONFIG_GDB_DEBUG)) /* SIMCALL is NOP in hw? */
 	//  In the simulator (ISS), let the debugger (if any is attached)
 	//  handle the debug exception, else simply stop the simulation:
 	//
-	wsr	a2, EXCSAVE+XCHAL_DEBUGLEVEL	// save a2 where simulator expects it
+	simcall	// have ISS handle the debug exception
-	movi	a2, SYS_gdb_enter_sktloop
-	simcall					// have ISS handle the debug exception
 # endif
-# ifndef SIMULATOR
+# if (!defined(SIMULATOR) && !defined(CONFIG_GDB_DEBUG))
 	//  For hardware, this code does not handle debug exceptions.
 	//  To implement a target-side debug monitor, replace this
 	//  vector with a real one that uses target-specific facilities
 	//  to communicate with the debugger.
 	//  
 1:
-#  if XCHAL_HAVE_INTERRUPTS
+	// unexpected debug exception, loop in low-power mode
-	//waiti	XCHAL_DEBUGLEVEL // unexpected debug exception, loop in low-power mode
+	//waiti	XCHAL_DEBUGLEVEL
-#  endif
 	j	1b		// infinite loop - unexpected debug exception
-# endif /*!SIMULATOR*/
+# endif /*!SIMULATOR && !CONFIG_GDB_DEBUG*/
+
+#if defined(CONFIG_GDB_DEBUG)
+	xsr	a2, DEBUG_EXCSAVE
+	jx	a2
+#endif
 
 	.end	literal_prefix
 	.size	_DebugExceptionVector, . - _DebugExceptionVector
 
 #endif /* XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS */
-

src/gdb/Makefile.am

@@ -0,0 +1,19 @@
+noinst_LIBRARIES = libgdb.a
+
+libgdb_a_SOURCES = \
+	init.S
+
+libgdb_a_CFLAGS = \
+	$(AM_CFLAGS) \
+	$(ARCH_CFLAGS) \
+	$(ARCH_INCDIR) \
+	$(PLATFORM_INCDIR) \
+	$(SOF_INCDIR)
+
+libgdb_a_CCASFLAGS = \
+	$(ARCH_INCDIR) \
+	$(ASFLAGS) \
+	$(ARCH_ASFLAGS) \
+	$(PLATFORM_INCDIR) \
+	$(ARCH_INCDIR) \
+	$(SOF_INCDIR)

src/gdb/init.S

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of the Intel Corporation nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Marcin Rajwa <marcin.rajwa@linux.intel.com>
+ *
+ * Init debug exeption and enable global breakpoints.
+ *
+ */
+
+#include <sof/gdb/xtensa-defs.h>
+
+.text
+.global initDebugException
+.align	4
+
+initDebugException:
+	entry	a1, 16
+
+	movi	a3, DebugExceptionEntry
+	wsr	a3, DEBUG_EXCSAVE
+
+	//enable breakpoints
+	movi a3, 1
+	wsr  a3, IBREAKENABLE
+
+	isync
+	rsync
+	retw
+
+.size	initDebugException, . - initDebugException

src/include/sof/gdb/Makefile.am

@@ -0,0 +1,2 @@
+noinst_HEADERS = \
+	xtensa-defs.h

src/include/sof/gdb/xtensa-defs.h

@@ -0,0 +1,16 @@
+#ifndef XTENSA_DEFS_H
+#define XTENSA_DEFS_H
+
+#include <xtensa/specreg.h>
+#include <xtensa/config/core-isa.h>
+#include <xtensa/corebits.h>
+#include <config.h>
+
+#define _AREG0		256
+
+#define STACK_SIZE	1024
+#define DEBUG_PC	(EPC + XCHAL_DEBUGLEVEL)
+#define DEBUG_EXCSAVE	(EXCSAVE + XCHAL_DEBUGLEVEL)
+#define DEBUG_PS	(EPS + XCHAL_DEBUGLEVEL)
+
+#endif /* XTENSA_DEFS_H */

src/platform/intel/cavs/platform.c

@@ -245,7 +245,7 @@ static void platform_memory_windows_init(void)
 	/* window2, for debug */
 	io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
 	io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
-		| DMWBA_READONLY | DMWBA_ENABLE);
+		| DMWBA_ENABLE);
 	bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
 	dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);