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interrupt: use CONFIG_INTERRUPT_x options 

Uses CONFIG_INTERRUPT_x options to conditionally build interrupt
drivers' code. These definitions should only be used in interrupt
drivers and platform interrupt headers. In case there is a need
to use additional interrupt level the appropriate kConfig option
should be selected. Otherwise the build will fail.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda 2019-10-01 12:59:30 +02:00 committed by Tomasz Lauda
parent 9c9db8b76e
commit 6ffd5f3fef
15 changed files with 669 additions and 324 deletions
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8
src/arch/xtensa/CMakeLists.txt
View File

@ -165,10 +165,18 @@ add_local_sources(sof
target_link_libraries(sof_static_libraries INTERFACE xtos)
target_link_libraries(sof_static_libraries INTERFACE hal)
if(CONFIG_INTERRUPT_LEVEL_2)
target_link_libraries(sof_static_libraries INTERFACE xlevel2)
endif()
if(CONFIG_INTERRUPT_LEVEL_3)
target_link_libraries(sof_static_libraries INTERFACE xlevel3)
endif()
if(CONFIG_INTERRUPT_LEVEL_4)
target_link_libraries(sof_static_libraries INTERFACE xlevel4)
endif()
if(CONFIG_INTERRUPT_LEVEL_5)
target_link_libraries(sof_static_libraries INTERFACE xlevel5)
endif()
if(build_bootloader)
add_local_sources(sof main-entry.S)

10
src/arch/xtensa/init.c
View File

@ -70,11 +70,21 @@ static void initialize_pointers_per_core(void)
p = &core_data->thread_data_ptr->xtos_ptrs;
p->xtos_interrupt_ctx = &core_data->xtos_interrupt_ctx;
p->xtos_saved_sp = &core_data->xtos_saved_sp;
#if CONFIG_INTERRUPT_LEVEL_1
p->xtos_stack_for_interrupt_1 = core_data->xtos_stack_for_interrupt_1;
#endif
#if CONFIG_INTERRUPT_LEVEL_2
p->xtos_stack_for_interrupt_2 = core_data->xtos_stack_for_interrupt_2;
#endif
#if CONFIG_INTERRUPT_LEVEL_3
p->xtos_stack_for_interrupt_3 = core_data->xtos_stack_for_interrupt_3;
#endif
#if CONFIG_INTERRUPT_LEVEL_4
p->xtos_stack_for_interrupt_4 = core_data->xtos_stack_for_interrupt_4;
#endif
#if CONFIG_INTERRUPT_LEVEL_5
p->xtos_stack_for_interrupt_5 = core_data->xtos_stack_for_interrupt_5;
#endif
#if CONFIG_SMP
p->xtos_enabled = &core_data->xtos_int_data.xtos_enabled;
p->xtos_intstruct = &core_data->xtos_int_data;

29
src/arch/xtensa/xtos/CMakeLists.txt
View File

@ -4,11 +4,6 @@ set(VECTOR_DEFS
-D__SPLIT__vector
-D__SPLIT__handler
-D__SPLIT__user
-D__SPLIT__level1int
-D__SPLIT__level2
-D__SPLIT__level3
-D__SPLIT__level4
-D__SPLIT__level5
)
# Builds lib for each level from the same source files
@ -28,7 +23,29 @@ function(sof_xtos_add_level level)
)
endfunction()
set(levels 2 3 4 5)
if(CONFIG_INTERRUPT_LEVEL_1)
list(APPEND VECTOR_DEFS -D__SPLIT__level1int)
endif()
if(CONFIG_INTERRUPT_LEVEL_2)
list(APPEND VECTOR_DEFS -D__SPLIT__level2)
list(APPEND levels 2)
endif()
if(CONFIG_INTERRUPT_LEVEL_3)
list(APPEND VECTOR_DEFS -D__SPLIT__level3)
list(APPEND levels 3)
endif()
if(CONFIG_INTERRUPT_LEVEL_4)
list(APPEND VECTOR_DEFS -D__SPLIT__level4)
list(APPEND levels 4)
endif()
if(CONFIG_INTERRUPT_LEVEL_5)
list(APPEND VECTOR_DEFS -D__SPLIT__level5)
list(APPEND levels 5)
endif()
foreach(level ${levels})
sof_xtos_add_level(${level})

10
src/arch/xtensa/xtos/xtos-structs.h
View File

@ -28,11 +28,21 @@ struct xtos_core_data {
#if CONFIG_SMP
struct XtosInterruptStructure xtos_int_data;
#endif
#if CONFIG_INTERRUPT_LEVEL_1
uint8_t xtos_stack_for_interrupt_1[SOF_STACK_SIZE];
#endif
#if CONFIG_INTERRUPT_LEVEL_2
uint8_t xtos_stack_for_interrupt_2[SOF_STACK_SIZE];
#endif
#if CONFIG_INTERRUPT_LEVEL_3
uint8_t xtos_stack_for_interrupt_3[SOF_STACK_SIZE];
#endif
#if CONFIG_INTERRUPT_LEVEL_4
uint8_t xtos_stack_for_interrupt_4[SOF_STACK_SIZE];
#endif
#if CONFIG_INTERRUPT_LEVEL_5
uint8_t xtos_stack_for_interrupt_5[SOF_STACK_SIZE];
#endif
xtos_task_context xtos_interrupt_ctx;
uintptr_t xtos_saved_sp;
struct thread_data *thread_data_ptr;

22
src/drivers/intel/baytrail/interrupt.c
View File

@ -8,6 +8,7 @@
#include <sof/drivers/interrupt.h>
#include <sof/lib/shim.h>
#include <config.h>
#include <stdint.h>
void platform_interrupt_init(void) {}
@ -21,14 +22,26 @@ void platform_interrupt_set(uint32_t irq)
void platform_interrupt_clear(uint32_t irq, uint32_t mask)
{
switch (irq) {
case IRQ_NUM_EXT_PMC:
case IRQ_NUM_EXT_IA:
#if CONFIG_INTERRUPT_LEVEL_1
case IRQ_NUM_SOFTWARE2:
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_SOFTWARE3:
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_SOFTWARE4:
case IRQ_NUM_SOFTWARE5:
#endif
#if CONFIG_INTERRUPT_LEVEL_4
case IRQ_NUM_EXT_PMC:
case IRQ_NUM_EXT_IA:
#endif
#if CONFIG_INTERRUPT_LEVEL_1 || CONFIG_INTERRUPT_LEVEL_2 || \
CONFIG_INTERRUPT_LEVEL_3 || CONFIG_INTERRUPT_LEVEL_4
arch_interrupt_clear(irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_5
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_PISR, mask << 3);
arch_interrupt_clear(irq);
@ -66,6 +79,7 @@ void platform_interrupt_clear(uint32_t irq, uint32_t mask)
shim_write(SHIM_PISRH, mask << 10);
arch_interrupt_clear(irq);
break;
#endif
#endif
default:
break;
@ -80,6 +94,7 @@ uint32_t platform_interrupt_get_enabled(void)
void interrupt_mask(uint32_t irq, unsigned int cpu)
{
#if CONFIG_INTERRUPT_LEVEL_5
switch (irq) {
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_PIMR, 1 << 3);
@ -113,10 +128,12 @@ void interrupt_mask(uint32_t irq, unsigned int cpu)
default:
break;
}
#endif
}
void interrupt_unmask(uint32_t irq, unsigned int cpu)
{
#if CONFIG_INTERRUPT_LEVEL_5
switch (irq) {
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 3));
@ -150,4 +167,5 @@ void interrupt_unmask(uint32_t irq, unsigned int cpu)
default:
break;
}
#endif
}

50
src/drivers/intel/cavs/interrupt.c
View File

@ -13,6 +13,7 @@
#include <sof/lib/shim.h>
#include <sof/list.h>
#include <sof/spinlock.h>
#include <config.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
@ -24,10 +25,18 @@
*/
#define LVL2_MAX_TRIES 1000
#if CONFIG_INTERRUPT_LEVEL_2
char irq_name_level2[] = "level2";
#endif
#if CONFIG_INTERRUPT_LEVEL_3
char irq_name_level3[] = "level3";
#endif
#if CONFIG_INTERRUPT_LEVEL_4
char irq_name_level4[] = "level4";
#endif
#if CONFIG_INTERRUPT_LEVEL_5
char irq_name_level5[] = "level5";
#endif
/*
* The level2 handler attempts to try and fairly service interrupt sources by
@ -110,25 +119,33 @@ static inline void irq_lvl2_handler(void *data, int level, uint32_t ilxsd,
REG_IRQ_IL##n##SD(core), \
REG_IRQ_IL##n##MSD(core))
#if CONFIG_INTERRUPT_LEVEL_2
static void irq_lvl2_level2_handler(void *data)
{
IRQ_LVL2_HANDLER(2);
}
#endif
#if CONFIG_INTERRUPT_LEVEL_3
static void irq_lvl2_level3_handler(void *data)
{
IRQ_LVL2_HANDLER(3);
}
#endif
#if CONFIG_INTERRUPT_LEVEL_4
static void irq_lvl2_level4_handler(void *data)
{
IRQ_LVL2_HANDLER(4);
}
#endif
#if CONFIG_INTERRUPT_LEVEL_5
static void irq_lvl2_level5_handler(void *data)
{
IRQ_LVL2_HANDLER(5);
}
#endif
uint32_t platform_interrupt_get_enabled(void)
{
@ -157,18 +174,26 @@ static void irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
{
/* mask external interrupt bit */
switch (desc->irq) {
#if CONFIG_INTERRUPT_LEVEL_5
case IRQ_NUM_EXT_LEVEL5:
irq_write(REG_IRQ_IL5MSD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_4
case IRQ_NUM_EXT_LEVEL4:
irq_write(REG_IRQ_IL4MSD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_EXT_LEVEL3:
irq_write(REG_IRQ_IL3MSD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_EXT_LEVEL2:
irq_write(REG_IRQ_IL2MSD(core), 1 << irq);
break;
#endif
}
}
@ -176,18 +201,26 @@ static void irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
{
/* unmask external interrupt bit */
switch (desc->irq) {
#if CONFIG_INTERRUPT_LEVEL_5
case IRQ_NUM_EXT_LEVEL5:
irq_write(REG_IRQ_IL5MCD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_4
case IRQ_NUM_EXT_LEVEL4:
irq_write(REG_IRQ_IL4MCD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_EXT_LEVEL3:
irq_write(REG_IRQ_IL3MCD(core), 1 << irq);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_EXT_LEVEL2:
irq_write(REG_IRQ_IL2MCD(core), 1 << irq);
break;
#endif
}
}
@ -198,31 +231,42 @@ static const struct irq_cascade_ops irq_ops = {
/* DSP internal interrupts */
static const struct irq_cascade_tmpl dsp_irq[] = {
#if CONFIG_INTERRUPT_LEVEL_2
{
.name = irq_name_level2,
.irq = IRQ_NUM_EXT_LEVEL2,
.handler = irq_lvl2_level2_handler,
.ops = &irq_ops,
.global_mask = false,
}, {
},
#endif
#if CONFIG_INTERRUPT_LEVEL_3
{
.name = irq_name_level3,
.irq = IRQ_NUM_EXT_LEVEL3,
.handler = irq_lvl2_level3_handler,
.ops = &irq_ops,
.global_mask = false,
}, {
},
#endif
#if CONFIG_INTERRUPT_LEVEL_4
{
.name = irq_name_level4,
.irq = IRQ_NUM_EXT_LEVEL4,
.handler = irq_lvl2_level4_handler,
.ops = &irq_ops,
.global_mask = false,
}, {
},
#endif
#if CONFIG_INTERRUPT_LEVEL_5
{
.name = irq_name_level5,
.irq = IRQ_NUM_EXT_LEVEL5,
.handler = irq_lvl2_level5_handler,
.ops = &irq_ops,
.global_mask = false,
},
#endif
};
void platform_interrupt_set(uint32_t irq)

26
src/drivers/intel/haswell/interrupt.c
View File

@ -8,6 +8,7 @@
#include <sof/drivers/interrupt.h>
#include <sof/lib/shim.h>
#include <config.h>
#include <stdint.h>
void platform_interrupt_init(void) {}
@ -21,15 +22,24 @@ void platform_interrupt_set(uint32_t irq)
void platform_interrupt_clear(uint32_t irq, uint32_t mask)
{
switch (irq) {
case IRQ_NUM_EXT_DMAC0:
case IRQ_NUM_EXT_DMAC1:
#if CONFIG_INTERRUPT_LEVEL_1
case IRQ_NUM_EXT_SSP0:
case IRQ_NUM_EXT_SSP1:
case IRQ_NUM_EXT_IA:
case IRQ_NUM_SOFTWARE1:
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_EXT_DMAC0:
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_EXT_DMAC1:
case IRQ_NUM_SOFTWARE2:
#endif
#if CONFIG_INTERRUPT_LEVEL_1 || CONFIG_INTERRUPT_LEVEL_2 || \
CONFIG_INTERRUPT_LEVEL_3
arch_interrupt_clear(irq);
break;
#endif
default:
break;
}
@ -44,18 +54,24 @@ uint32_t platform_interrupt_get_enabled(void)
void interrupt_mask(uint32_t irq, unsigned int cpu)
{
switch (irq) {
#if CONFIG_INTERRUPT_LEVEL_1
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_IMRD, SHIM_IMRD_SSP0);
break;
case IRQ_NUM_EXT_SSP1:
shim_write(SHIM_IMRD, SHIM_IMRD_SSP1);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_EXT_DMAC0:
shim_write(SHIM_IMRD, SHIM_IMRD_DMAC0);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_EXT_DMAC1:
shim_write(SHIM_IMRD, SHIM_IMRD_DMAC1);
break;
#endif
default:
break;
}
@ -64,18 +80,24 @@ void interrupt_mask(uint32_t irq, unsigned int cpu)
void interrupt_unmask(uint32_t irq, unsigned int cpu)
{
switch (irq) {
#if CONFIG_INTERRUPT_LEVEL_1
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP0);
break;
case IRQ_NUM_EXT_SSP1:
shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP1);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_2
case IRQ_NUM_EXT_DMAC0:
shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC0);
break;
#endif
#if CONFIG_INTERRUPT_LEVEL_3
case IRQ_NUM_EXT_DMAC1:
shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC1);
break;
#endif
default:
break;
}

130
src/platform/apollolake/include/platform/drivers/interrupt.h
View File

@ -11,31 +11,33 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 32
/* IRQ numbers - wrt Tensilica DSP */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
#define IRQ_NUM_TIMER1 1 /* level 1 */
#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
#define IRQ_NUM_TIMER2 5 /* level 2 */
#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
#define IRQ_NUM_NMI 20 /* level 7 */
/* IRQ Level 2 bits */
#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
@ -49,21 +51,6 @@
#define IRQ_BIT_LVL2_CSME_IPC 6
#define IRQ_BIT_LVL2_PMC_IPC 5
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1(x) (24 + x)
#define IRQ_BIT_LVL5_LP_GP_DMA0(x) (16 + x)
#define IRQ_BIT_LVL5_DMIC(x) 6
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Level 2 Peripheral IRQ mappings */
#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0)
#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC
@ -74,45 +61,86 @@
#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE
#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* Level 3 Peripheral IRQ mappings */
#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER
#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel)
#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* Level 4 Peripheral IRQ mappings */
#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel)
#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1(x) (24 + x)
#define IRQ_BIT_LVL5_LP_GP_DMA0(x) (16 + x)
#define IRQ_BIT_LVL5_DMIC(x) 6
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Level 5 Peripheral IRQ mappings */
#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0(channel)
#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA1(channel)
#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x)
#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x)
#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
#endif
#define IRQ_NUM_NMI 20 /* level 7 */
#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */

73
src/platform/baytrail/include/platform/drivers/interrupt.h
View File

@ -10,18 +10,58 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
/* IRQ numbers */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* Level 1 */
#define IRQ_NUM_TIMER1 1 /* Level 1 */
#define IRQ_NUM_SOFTWARE1 2 /* Level 1 */
#define IRQ_NUM_SOFTWARE2 3 /* Level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_TIMER2 5 /* Level 2 */
#define IRQ_NUM_SOFTWARE3 6 /* Level 2 */
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_TIMER3 7 /* Level 3 */
#define IRQ_NUM_SOFTWARE4 8 /* Level 3 */
#define IRQ_NUM_SOFTWARE5 9 /* Level 3 */
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_EXT_IA 10 /* Level 4 */
#define IRQ_NUM_EXT_PMC 11 /* Level 4 */
#define IRQ_MASK_EXT_IA BIT(IRQ_NUM_EXT_IA)
#define IRQ_MASK_EXT_PMC BIT(IRQ_NUM_EXT_PMC)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE6 12 /* Level 5 */
#define IRQ_NUM_EXT_DMAC0 13 /* Level 5 */
#define IRQ_NUM_EXT_DMAC1 14 /* Level 5 */
@ -30,7 +70,6 @@
#define IRQ_NUM_EXT_SSP1 17 /* Level 5 */
#define IRQ_NUM_EXT_SSP2 18 /* Level 5 */
#define IRQ_NUM_EXT_DMAC2 19 /* Level 5 */
#define IRQ_NUM_NMI 20 /* Level 7 */
/* SSP 3,4,5 share PHY IRQs with SSP 0,1,2 respectively but we give them a
* virtual number in order to differentiate from SSP0, 1 and 2 IRQs
@ -42,26 +81,18 @@
#define IRQ_NUM_EXT_SSP4 (IRQ_CHT_SSP_OFFSET + IRQ_NUM_EXT_SSP1)
#define IRQ_NUM_EXT_SSP5 (IRQ_CHT_SSP_OFFSET + IRQ_NUM_EXT_SSP2)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
#define IRQ_MASK_EXT_PMC (1 << IRQ_NUM_EXT_PMC)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
#define IRQ_MASK_EXT_TIMER (1 << IRQ_NUM_EXT_TIMER)
#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
#define IRQ_MASK_EXT_SSP2 (1 << IRQ_NUM_EXT_SSP2)
#define IRQ_MASK_EXT_DMAC2 (1 << IRQ_NUM_EXT_DMAC2)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_DMAC0 BIT(IRQ_NUM_EXT_DMAC0)
#define IRQ_MASK_EXT_DMAC1 BIT(IRQ_NUM_EXT_DMAC1)
#define IRQ_MASK_EXT_TIMER BIT(IRQ_NUM_EXT_TIMER)
#define IRQ_MASK_EXT_SSP0 BIT(IRQ_NUM_EXT_SSP0)
#define IRQ_MASK_EXT_SSP1 BIT(IRQ_NUM_EXT_SSP1)
#define IRQ_MASK_EXT_SSP2 BIT(IRQ_NUM_EXT_SSP2)
#define IRQ_MASK_EXT_DMAC2 BIT(IRQ_NUM_EXT_DMAC2)
#endif
#define IRQ_NUM_NMI 20 /* Level 7 */
/* no nested interrupts */
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS

130
src/platform/cannonlake/include/platform/drivers/interrupt.h
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@ -12,31 +12,33 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 32
/* IRQ numbers - wrt Tensilica DSP */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
#define IRQ_NUM_TIMER1 1 /* level 1 */
#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
#define IRQ_NUM_TIMER2 5 /* level 2 */
#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
#define IRQ_NUM_NMI 20 /* level 7 */
/* IRQ Level 2 bits */
#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
@ -50,21 +52,6 @@
#define IRQ_BIT_LVL2_CSME_IPC 6
#define IRQ_BIT_LVL2_PMC_IPC 5
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 2 Peripheral IRQ mappings */
#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0)
#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC
@ -75,45 +62,86 @@
#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE
#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* Priority 3 Peripheral IRQ mappings */
#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER
#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel)
#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* Priority 4 Peripheral IRQ mappings */
#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel)
#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 5 Peripheral IRQ mappings */
#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x)
#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x)
#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
#endif
#define IRQ_NUM_NMI 20 /* level 7 */
#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */

63
src/platform/haswell/include/platform/drivers/interrupt.h
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@ -10,37 +10,68 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 0
/* IRQ numbers */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_EXT_SSP0 0 /* Level 1 */
#define IRQ_NUM_EXT_SSP1 1 /* Level 1 */
#define IRQ_NUM_EXT_OBFF 2 /* Level 1 */
#define IRQ_NUM_EXT_IA 4 /* Level 1 */
#define IRQ_NUM_TIMER1 6 /* Level 1 */
#define IRQ_NUM_SOFTWARE1 7 /* Level 1 */
#define IRQ_MASK_EXT_SSP0 BIT(IRQ_NUM_EXT_SSP0)
#define IRQ_MASK_EXT_SSP1 BIT(IRQ_NUM_EXT_SSP1)
#define IRQ_MASK_EXT_OBFF BIT(IRQ_NUM_EXT_OBFF)
#define IRQ_MASK_EXT_IA BIT(IRQ_NUM_EXT_IA)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_EXT_DMAC0 8 /* Level 2 */
#define IRQ_MASK_EXT_DMAC0 BIT(IRQ_NUM_EXT_DMAC0)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_EXT_DMAC1 9 /* Level 3 */
#define IRQ_NUM_TIMER2 10 /* Level 3 */
#define IRQ_NUM_SOFTWARE2 11 /* Level 3 */
#define IRQ_NUM_EXT_PARITY 12 /* Level 4 */
#define IRQ_NUM_TIMER3 13 /* Level 5 */
#define IRQ_NUM_NMI 14 /* Level 7 */
/* IRQ Masks */
#define IRQ_MASK_EXT_SSP0 (1 << IRQ_NUM_EXT_SSP0)
#define IRQ_MASK_EXT_SSP1 (1 << IRQ_NUM_EXT_SSP1)
#define IRQ_MASK_EXT_OBFF (1 << IRQ_NUM_EXT_OBFF)
#define IRQ_MASK_EXT_IA (1 << IRQ_NUM_EXT_IA)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_EXT_DMAC0 (1 << IRQ_NUM_EXT_DMAC0)
#define IRQ_MASK_EXT_DMAC1 (1 << IRQ_NUM_EXT_DMAC1)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_EXT_PARITY (1 << IRQ_NUM_EXT_PARITY)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_DMAC1 BIT(IRQ_NUM_EXT_DMAC1)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_EXT_PARITY 12 /* Level 4 */
#define IRQ_MASK_EXT_PARITY BIT(IRQ_NUM_EXT_PARITY)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_TIMER3 13 /* Level 5 */
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#endif
#define IRQ_NUM_NMI 14 /* Level 7 */
#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */

130
src/platform/icelake/include/platform/drivers/interrupt.h
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@ -12,31 +12,33 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 32
/* IRQ numbers - wrt Tensilica DSP */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
#define IRQ_NUM_TIMER1 1 /* level 1 */
#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
#define IRQ_NUM_TIMER2 5 /* level 2 */
#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
#define IRQ_NUM_NMI 20 /* level 7 */
/* IRQ Level 2 bits */
#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
@ -50,21 +52,6 @@
#define IRQ_BIT_LVL2_CSME_IPC 6
#define IRQ_BIT_LVL2_PMC_IPC 5
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 2 Peripheral IRQ mappings */
#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0)
#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC
@ -75,45 +62,86 @@
#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE
#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* Priority 3 Peripheral IRQ mappings */
#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER
#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel)
#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* Priority 4 Peripheral IRQ mappings */
#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel)
#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 5 Peripheral IRQ mappings */
#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x)
#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x)
#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
#endif
#define IRQ_NUM_NMI 20 /* level 7 */
#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */

52
src/platform/imx8/include/platform/drivers/interrupt.h
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@ -10,11 +10,22 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
/* IRQ numbers */
#define IRQ_NUM_TIMER0 2 /* Level 2 */
#define IRQ_NUM_TIMER1 3 /* Level 3 */
#define IRQ_NUM_MU 7 /* Level 2 */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 8 /* Level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_TIMER0 2 /* Level 2 */
#define IRQ_NUM_MU 7 /* Level 2 */
#define IRQ_NUM_SOFTWARE1 9 /* Level 2 */
#define IRQ_NUM_IRQSTR_DSP0 19 /* Level 2 */
#define IRQ_NUM_IRQSTR_DSP1 20 /* Level 2 */
@ -25,20 +36,27 @@
#define IRQ_NUM_IRQSTR_DSP6 25 /* Level 2 */
#define IRQ_NUM_IRQSTR_DSP7 26 /* Level 2 */
/* IRQ Masks */
#define IRQ_MASK_TIMER0 (1 << IRQ_NUM_TIMER0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_MU (1 << IRQ_NUM_MU)
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_IRQSTR_DSP0 (1 << IRQ_NUM_IRQSTR_DSP0)
#define IRQ_MASK_IRQSTR_DSP1 (1 << IRQ_NUM_IRQSTR_DSP1)
#define IRQ_MASK_IRQSTR_DSP2 (1 << IRQ_NUM_IRQSTR_DSP2)
#define IRQ_MASK_IRQSTR_DSP3 (1 << IRQ_NUM_IRQSTR_DSP3)
#define IRQ_MASK_IRQSTR_DSP4 (1 << IRQ_NUM_IRQSTR_DSP4)
#define IRQ_MASK_IRQSTR_DSP5 (1 << IRQ_NUM_IRQSTR_DSP5)
#define IRQ_MASK_IRQSTR_DSP6 (1 << IRQ_NUM_IRQSTR_DSP6)
#define IRQ_MASK_IRQSTR_DSP7 (1 << IRQ_NUM_IRQSTR_DSP7)
#define IRQ_MASK_TIMER0 BIT(IRQ_NUM_TIMER0)
#define IRQ_MASK_MU BIT(IRQ_NUM_MU)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_IRQSTR_DSP0 BIT(IRQ_NUM_IRQSTR_DSP0)
#define IRQ_MASK_IRQSTR_DSP1 BIT(IRQ_NUM_IRQSTR_DSP1)
#define IRQ_MASK_IRQSTR_DSP2 BIT(IRQ_NUM_IRQSTR_DSP2)
#define IRQ_MASK_IRQSTR_DSP3 BIT(IRQ_NUM_IRQSTR_DSP3)
#define IRQ_MASK_IRQSTR_DSP4 BIT(IRQ_NUM_IRQSTR_DSP4)
#define IRQ_MASK_IRQSTR_DSP5 BIT(IRQ_NUM_IRQSTR_DSP5)
#define IRQ_MASK_IRQSTR_DSP6 BIT(IRQ_NUM_IRQSTR_DSP6)
#define IRQ_MASK_IRQSTR_DSP7 BIT(IRQ_NUM_IRQSTR_DSP7)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_TIMER1 3 /* Level 3 */
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#endif
/* 32 HW interrupts + 8 IRQ_STEER lines each with 64 interrupts */
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS

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src/platform/suecreek/include/platform/drivers/interrupt.h
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@ -12,33 +12,34 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <sof/drivers/interrupt-map.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 32
/* IRQ numbers - wrt Tensilica DSP */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
#define IRQ_NUM_TIMER1 1 /* level 1 */
#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
#define IRQ_NUM_TIMER2 5 /* level 2 */
#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
#define IRQ_NUM_NMI 20 /* level 7 */
/* IRQ Level 2 bits */
#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
@ -48,27 +49,10 @@
#define IRQ_BIT_LVL2_SHA256 16
#define IRQ_BIT_LVL2_L2_CACHE 15
#define IRQ_BIT_LVL2_IDC 8
#define IRQ_BIT_LVL2_USB 7
#define IRQ_BIT_LVL2_HOST_IPC 7
#define IRQ_BIT_LVL2_CSME_IPC 6
#define IRQ_BIT_LVL2_PMC_IPC 5
/* IRQ Level 3 bits EXT10 */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
#define IRQ_BIT_LVL3_HPGPDMA 15
/* IRQ Level 4 bits EXT13 */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* IRQ Level 5 bits EXT16 */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 2 Peripheral IRQ mappings */
#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0)
#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC
@ -79,46 +63,86 @@
#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE
#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* Priority 3 Peripheral IRQ mappings */
#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER
#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel)
#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* Priority 4 Peripheral IRQ mappings */
#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel)
#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 5 Peripheral IRQ mappings */
#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x)
#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x)
#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
#endif
#define IRQ_NUM_NMI 20 /* level 7 */
/* platform interrupt control */
#define SUE_DW_ICTL_BASE_ADDR 0x00081800

130
src/platform/tigerlake/include/platform/drivers/interrupt.h
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@ -12,31 +12,33 @@
#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
#define __PLATFORM_DRIVERS_INTERRUPT_H__
#include <sof/bit.h>
#include <config.h>
#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
#define PLATFORM_IRQ_CHILDREN 32
/* IRQ numbers - wrt Tensilica DSP */
#if CONFIG_INTERRUPT_LEVEL_1
#define IRQ_NUM_SOFTWARE0 0 /* level 1 */
#define IRQ_NUM_TIMER1 1 /* level 1 */
#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */
#define IRQ_NUM_SOFTWARE1 3 /* level 1 */
#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1)
#endif
#if CONFIG_INTERRUPT_LEVEL_2
#define IRQ_NUM_SOFTWARE2 4 /* level 2 */
#define IRQ_NUM_TIMER2 5 /* level 2 */
#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */
#define IRQ_NUM_SOFTWARE3 7 /* level 2 */
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
#define IRQ_NUM_NMI 20 /* level 7 */
/* IRQ Level 2 bits */
#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24)
@ -50,21 +52,6 @@
#define IRQ_BIT_LVL2_CSME_IPC 6
#define IRQ_BIT_LVL2_PMC_IPC 5
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 2 Peripheral IRQ mappings */
#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0)
#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC
@ -75,45 +62,86 @@
#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE
#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256
#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3)
#endif
#if CONFIG_INTERRUPT_LEVEL_3
#define IRQ_NUM_SOFTWARE4 8 /* level 3 */
#define IRQ_NUM_TIMER3 9 /* level 3 */
#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */
#define IRQ_NUM_SOFTWARE5 11 /* level 3 */
/* IRQ Level 3 bits */
#define IRQ_BIT_LVL3_CODE_LOADER 31
#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x)
/* Priority 3 Peripheral IRQ mappings */
#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER
#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel)
#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5)
#endif
#if CONFIG_INTERRUPT_LEVEL_4
#define IRQ_NUM_SOFTWARE6 12 /* level 4 */
#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */
#define IRQ_NUM_SOFTWARE7 14 /* level 4 */
/* IRQ Level 4 bits */
#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x)
#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x)
/* Priority 4 Peripheral IRQ mappings */
#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel)
#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel)
#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7)
#endif
#if CONFIG_INTERRUPT_LEVEL_5
#define IRQ_NUM_SOFTWARE8 15 /* level 5 */
#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */
#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */
#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */
#define IRQ_NUM_SOFTWARE9 19 /* level 5 */
/* IRQ Level 5 bits */
#define IRQ_BIT_LVL5_LP_GP_DMA1 15
#define IRQ_BIT_LVL5_LP_GP_DMA0 16
#define IRQ_BIT_LVL5_DMIC(x) 8
#define IRQ_BIT_LVL5_SSP(x) (0 + x)
/* Priority 5 Peripheral IRQ mappings */
#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0
#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x)
#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x)
#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9)
/* IRQ Masks */
#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0)
#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1)
#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1)
#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1)
#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2)
#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2)
#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2)
#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3)
#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4)
#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3)
#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3)
#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5)
#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6)
#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4)
#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7)
#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8)
#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5)
#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6)
#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7)
#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9)
#endif
#define IRQ_NUM_NMI 20 /* level 7 */
#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */