mirror of https://github.com/thesofproject/sof.git
topology1: sof-cavs-nocodec: fix documentation
Fix the documentation to match actual topology definition. The comments did not include addition of mixers nor the capture PCMs. Also many comments reflect a fixed core id that is no longer accurate. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit is contained in:
Kai Vehmanen
Liam Girdwood
parent
ec63f3a70e
commit
601cbc061d
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@ -94,9 +94,17 @@ define(DAI_BITS, `s24le')
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#
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# Define the pipelines
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#
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# PCM0 <---> volume <----> SSP0
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# PCM1 <---> Volume <----> SSP1
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# PCM2 <---> volume <----> SSP2
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# PCM0 <---> Volume <---\
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# +- Mixer <----> SSP0
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# PCM3 <---> Volume <---/
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# PCM1 <---> Volume <----> Mixer <----> SSP1
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# PCM2 <---> volume <----> Mixer <----> SSP2
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#
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# SSP0 <---> Volume <----> PCM0
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# SSP1 <---> Volume <----> PCM1
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# SSP2 <---> Volume <----> PCM2
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# DMIC0 <--> IIR <----> PCM10
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# DMIC1 <--> IIR <----> PCM11
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#
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dnl PIPELINE_PCM_ADD(pipeline,
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@ -106,21 +114,21 @@ dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
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dnl time_domain, sched_comp)
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# Volume switch capture pipeline 2 on PCM 0 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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2, 0, 2, PIPE_BITS,
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1000, 0, SSP0_CORE_ID,
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48000, 48000, 48000)
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# Volume switch capture pipeline 4 on PCM 1 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 1 with priority 0
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# Set 1000us deadline on core SSP1_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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4, 1, 2, PIPE_BITS,
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1000, 0, SSP1_CORE_ID,
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48000, 48000, 48000)
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# Volume switch capture pipeline 6 on PCM 2 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline with priority 0 on core 0
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# Set 1000us deadline with priority 0 on core SSP2_CORE_ID
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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6, 2, 2, PIPE_BITS,
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1000, 0, SSP2_CORE_ID,
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@ -136,7 +144,7 @@ dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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# playback DAI is SSP0 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP0_CORE_ID
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# The 'NOT_USED_IGNORED' is due to dependencies and is adjusted later with an explicit dapm line.
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DAI_ADD(sof/pipe-mixer-dai-playback.m4,
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1, SSP, SSP0_IDX, NoCodec-0,
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@ -144,7 +152,7 @@ DAI_ADD(sof/pipe-mixer-dai-playback.m4,
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1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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7, 0, 2, PIPE_BITS,
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1000, 0, SSP0_CORE_ID,
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@ -153,7 +161,7 @@ PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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# Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0.
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0.
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# TODO: Modify pipeline deadline to account for deep buffering
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ifelse(PLATFORM, `bxt', `',
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`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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@ -164,21 +172,21 @@ ifelse(PLATFORM, `bxt', `',
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PIPELINE_PLAYBACK_SCHED_COMP_1)')
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# capture DAI is SSP0 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP0_IDX
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, SSP, SSP0_IDX, NoCodec-0,
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PIPELINE_SINK_2, 2, DAI_BITS,
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1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is SSP1 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP1_CORE_ID
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DAI_ADD(sof/pipe-mixer-dai-playback.m4,
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3, SSP, SSP1_IDX, NoCodec-1,
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NOT_USED_IGNORED, 2, DAI_BITS,
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1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 8 on PCM 1 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0
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# Set 1000us deadline on core SSP1_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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8, 1, 2, PIPE_BITS,
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1000, 0, SSP1_CORE_ID,
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@ -187,21 +195,21 @@ PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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PIPELINE_PLAYBACK_SCHED_COMP_3)
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# capture DAI is SSP1 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP1_CORE_ID
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DAI_ADD(sof/pipe-dai-capture.m4,
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4, SSP, SSP1_IDX, NoCodec-1,
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PIPELINE_SINK_4, 2, DAI_BITS,
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1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is SSP2 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP2_CORE_ID
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DAI_ADD(sof/pipe-mixer-dai-playback.m4,
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5, SSP, SSP2_IDX, NoCodec-2,
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NOT_USED_IGNORED, 2, DAI_BITS,
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1000, 0, SSP2_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 9 on PCM 2 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0
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# Set 1000us deadline on core SSP2_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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9, 2, 2, PIPE_BITS,
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1000, 0, SSP2_CORE_ID,
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@ -210,7 +218,7 @@ PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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PIPELINE_PLAYBACK_SCHED_COMP_5)
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# Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core 2 with priority 0.
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# Set 1000us deadline on core SSP2_CORE_ID with priority 0.
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# TODO: Modify pipeline deadline to account for deep buffering
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ifelse(PLATFORM, `bxt',
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`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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@ -221,7 +229,7 @@ ifelse(PLATFORM, `bxt',
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PIPELINE_PLAYBACK_SCHED_COMP_5)')
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# capture DAI is SSP2 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core 0
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP2_CORE_ID
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DAI_ADD(sof/pipe-dai-capture.m4,
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6, SSP, SSP2_IDX, NoCodec-2,
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PIPELINE_SINK_6, 2, DAI_BITS,
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