mirror of https://github.com/thesofproject/sof.git
Topology: Add simple topologies (no KWD) for CML RT1011 RT5682
This patch is based on sof-cml-rt1011-rt5682.m4 but omits the hard coded keyword pipeline and replaces it with a generic 16 kHz capture pipeline. The use of intel-generic-dmic.m4 to set up the capture pipeline simplifies the topology a lot. This change makes the topology for CML I2S quite similar to sof-hda-generic to add audio processing. All endpoint processing can be defined from top level CMakeLists.txt with macros HSMICPROC, HSEARPROC, SPKPROC, DMICPROC, DMIC16KPROC. A sample topology with equalizers in headset and speaker paths is added. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This commit is contained in:
Seppo Ingalsuo
Liam Girdwood
parent
969f370a36
commit
5b9a82deff
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@ -14,6 +14,8 @@ set(TPLGS
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"sof-cml-src-rt5682\;sof-cml-src-rt5682"
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"sof-hda-asrc\;sof-hda-asrc-2ch\;-DCHANNELS=2"
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"sof-tgl-nocodec-ci\;sof-tgl-nocodec-ci"
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"sof-cml-rt1011-rt5682-nokwd\;sof-cml-rt1011-rt5682-nokwd\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4"
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"sof-cml-rt1011-rt5682-nokwd\;sof-cml-rt1011-rt5682-eq\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DHSEARPROC=eq-iir-eq-fir-volume\;-DHSMICPROC=eq-fir-volume\;-DSPKPROC=eq-iir-eq-fir-volume"
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)
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@ -0,0 +1,203 @@
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#
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# Topology for Cometlake with RT5682 codec and RT1011 class-D speaker amp
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#
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# Include topology builder
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include(`abi.h')
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`ssp.m4')
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include(`hda.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Platform specific DSP configuration
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include(`platform/intel/cml.m4')
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# if XPROC is not defined, define with default pipe
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ifdef(`HSMICPROC', , `define(HSMICPROC, volume)')
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ifdef(`HSEARPROC', , `define(HSEARPROC, volume)')
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ifdef(`SPKPROC', , `define(SPKPROC, volume)')
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ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)')
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ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)')
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DEBUG_START
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# Define pipeline id for intel-generic-dmic.m4
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# to generate dmic setting
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ifelse(CHANNELS, `0', ,
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`
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define(DMIC_PCM_48k_ID, `1')
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define(DMIC_PIPELINE_48k_ID, `3')
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define(DMIC_DAI_LINK_48k_ID, `1')
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define(DMIC_PCM_16k_ID, `8')
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define(DMIC_PIPELINE_16k_ID, `8')
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define(DMIC_DAI_LINK_16k_ID, `2')
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include(`platform/intel/intel-generic-dmic.m4')
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'
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)
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#
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# Define the pipelines
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#
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# PCM0 ----> HSEARPROC (pipe 1) ----> SSP (SSP_INDEX, BE link 0)
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# PCM0 <---- HSMICPROC (pipe 2) <---- SSP (SSP_INDEX, BE link 0)
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# PCM1 <---- DMICPROC (pipe 3) <---- DMIC01 (dmic0 capture, , BE link 1)
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# PCM2 ----> volume (pipe 4) ----> iDisp1 (HDMI/DP playback, BE link 3)
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# PCM3 ----> volume (pipe 5) ----> iDisp2 (HDMI/DP playback, BE link 4)
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# PCM4 ----> volume (pipe 6) ----> iDisp3 (HDMI/DP playback, BE link 5)
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# PCM5 ----> SPKPROC (pipe 7) ----> SSP1 (speaker - rt1011, BE link 5)
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# PCM8 <---- DMIC16KPROC (pipe 8) <---- DMIC1 (dmic16k, BE link 2)
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl period, priority, core,
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dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
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dnl time_domain, sched_comp)
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le.
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# Schedule 1000us deadline on core 0 with priority 0
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ifdef(`HSEARPROC_FILTER1', `define(PIPELINE_FILTER1, HSEARPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')')
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ifdef(`HSEARPROC_FILTER2', `define(PIPELINE_FILTER2, HSEARPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')')
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PIPELINE_PCM_ADD(sof/pipe-HSEARPROC-playback.m4,
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1, 0, 2, s24le,
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1000, 0, 0,
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48000, 48000, 48000)
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undefine(`PIPELINE_FILTER1')
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undefine(`PIPELINE_FILTER2')
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# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le.
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# Schedule 1000us deadline on core 0 with priority 0
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ifdef(`HSMICPROC_FILTER1', `define(PIPELINE_FILTER1, HSMICPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')')
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ifdef(`HSMICPROC_FILTER2', `define(PIPELINE_FILTER2, HSMICPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')')
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PIPELINE_PCM_ADD(sof/pipe-HSMICPROC-capture.m4,
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2, 0, 2, s24le,
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1000, 0, 0,
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48000, 48000, 48000)
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undefine(`PIPELINE_FILTER1')
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undefine(`PIPELINE_FILTER2')
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# Low Latency playback pipeline 4 on PCM 2 using max 2 channels of s32le.
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# Schedule 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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4, 2, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 5 on PCM 3 using max 2 channels of s32le.
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# Schedule 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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5, 3, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 6 on PCM 4 using max 2 channels of s32le.
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# Schedule 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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6, 4, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 7 on PCM 5 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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ifdef(`SPKPROC_FILTER1', `define(PIPELINE_FILTER1, SPKPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')')
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ifdef(`SPKPROC_FILTER2', `define(PIPELINE_FILTER2, SPKPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')')
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PIPELINE_PCM_ADD(sof/pipe-SPKPROC-playback.m4,
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7, 5, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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undefine(`PIPELINE_FILTER1')
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undefine(`PIPELINE_FILTER2')
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#
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# DAIs configuration
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#
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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# playback DAI is SSP(SPP_INDEX) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, SSP, SSP_INDEX, SSP_NAME,
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PIPELINE_SOURCE_1, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# capture DAI is SSP(SSP_INDEX) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, SSP,SSP_INDEX, SSP_NAME,
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PIPELINE_SINK_2, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is SSP1 using 2 periods
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# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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7, SSP, 1, SSP1-Codec,
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PIPELINE_SOURCE_7, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp1 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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4, HDA, 0, iDisp1,
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PIPELINE_SOURCE_4, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp2 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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5, HDA, 1, iDisp2,
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PIPELINE_SOURCE_5, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp3 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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6, HDA, 2, iDisp3,
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PIPELINE_SOURCE_6, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# PCM Low Latency, id 0
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dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)
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PCM_DUPLEX_ADD(Port1, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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PCM_PLAYBACK_ADD(HDMI1, 2, PIPELINE_PCM_4)
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PCM_PLAYBACK_ADD(HDMI2, 3, PIPELINE_PCM_5)
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PCM_PLAYBACK_ADD(HDMI3, 4, PIPELINE_PCM_6)
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PCM_PLAYBACK_ADD(Speakers, 5, PIPELINE_PCM_7)
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#
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# BE configurations - overrides config in ACPI if present
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#
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#SSP SSP_INDEX (ID: 0)
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DAI_CONFIG(SSP, SSP_INDEX, 0, SSP_NAME,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, SSP_MCLK_RATE, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP_INDEX, 24)))
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DAI_CONFIG(SSP, SSP1_INDEX, 6, SSP1_NAME,
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SSP_CONFIG(DSP_A, SSP_CLOCK(mclk, SSP1_MCLK_RATE, codec_mclk_in),
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SSP_CLOCK(bclk, 4800000, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(4, 25, 3, 15),
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SSP_CONFIG_DATA(SET_SSP1_CONFIG_DATA)))
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# 3 HDMI/DP outputs (ID: 3,4,5)
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DAI_CONFIG(HDA, 0, 3, iDisp1,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2)))
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DAI_CONFIG(HDA, 1, 4, iDisp2,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2)))
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DAI_CONFIG(HDA, 2, 5, iDisp3,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2)))
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DEBUG_END
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