mirror of https://github.com/thesofproject/sof.git
platform: mt8195: add afe-platform support
Add memif data for afe Add common and regs header for afe Add afe platform for mt8195 audio/dsp AFE: the abbreviation for Audio Front End Signed-off-by: YC Hung <yc.hung@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
This commit is contained in:
Allen-KH Cheng
Liam Girdwood
parent
1b7f8ed2a6
commit
5b5936fba6
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: YC Hung <yc.hung@mediatek.com>
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#include <sof/common.h>
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#include <errno.h>
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#include <sof/drivers/afe-drv.h>
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#include <mt8195-afe-regs.h>
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#include <mt8195-afe-common.h>
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/*
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* AFE: Audio Front-End
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*
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* frontend (memif):
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* memory interface
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* UL (uplink for capture)
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* DL (downlink for playback)
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* backend:
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* TDM In
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* TMD out
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* DMIC
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* GASRC
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* etc.
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* interconn:
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* inter-connection,
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* connect frontends and backends as DSP path
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*/
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static const struct mtk_base_memif_data memif_data[MT8195_MEMIF_NUM] = {
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[MT8195_MEMIF_DL2] = {
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.name = "DL2",
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.id = MT8195_MEMIF_DL2,
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.reg_ofs_base = AFE_DL2_BASE,
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.reg_ofs_cur = AFE_DL2_CUR,
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.reg_ofs_end = AFE_DL2_END,
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.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
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.fs_shift = 10,
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.fs_maskbit = 0x1f,
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.mono_reg = -1,
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.mono_shift = -1,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 18,
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.hd_reg = AFE_DL2_CON0,
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.hd_shift = 5,
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.agent_disable_reg = AUDIO_TOP_CON5,
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.agent_disable_shift = 18,
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.ch_num_reg = AFE_DL2_CON0,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0x1f,
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.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
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.msb_shift = 18,
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.msb2_reg = AFE_NORMAL_END_ADR_MSB,
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.msb2_shift = 18,
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},
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[MT8195_MEMIF_DL3] = {
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.name = "DL3",
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.id = MT8195_MEMIF_DL3,
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.reg_ofs_base = AFE_DL3_BASE,
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.reg_ofs_cur = AFE_DL3_CUR,
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.reg_ofs_end = AFE_DL3_END,
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.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
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.fs_shift = 15,
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.fs_maskbit = 0x1f,
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.mono_reg = -1,
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.mono_shift = -1,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 19,
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.hd_reg = AFE_DL3_CON0,
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.hd_shift = 5,
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.agent_disable_reg = AUDIO_TOP_CON5,
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.agent_disable_shift = 19,
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.ch_num_reg = AFE_DL3_CON0,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0x1f,
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.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
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.msb_shift = 19,
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.msb2_reg = AFE_NORMAL_END_ADR_MSB,
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.msb2_shift = 19,
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},
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[MT8195_MEMIF_UL4] = {
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.name = "UL4",
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.id = MT8195_MEMIF_UL4,
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.reg_ofs_base = AFE_UL4_BASE,
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.reg_ofs_cur = AFE_UL4_CUR,
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.reg_ofs_end = AFE_UL4_END,
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.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
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.fs_shift = 15,
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.fs_maskbit = 0x1f,
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.mono_reg = AFE_UL4_CON0,
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.mono_shift = 1,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 4,
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.hd_reg = AFE_UL4_CON0,
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.hd_shift = 5,
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.agent_disable_reg = AUDIO_TOP_CON5,
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.agent_disable_shift = 3,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
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.msb_shift = 3,
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.msb2_reg = AFE_NORMAL_END_ADR_MSB,
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.msb2_shift = 3,
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},
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[MT8195_MEMIF_UL5] = {
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.name = "UL5",
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.id = MT8195_MEMIF_UL5,
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.reg_ofs_base = AFE_UL5_BASE,
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.reg_ofs_cur = AFE_UL5_CUR,
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.reg_ofs_end = AFE_UL5_END,
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.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
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.fs_shift = 20,
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.fs_maskbit = 0x1f,
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.mono_reg = AFE_UL5_CON0,
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.mono_shift = 1,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = 5,
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.hd_reg = AFE_UL5_CON0,
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.hd_shift = 5,
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.agent_disable_reg = AUDIO_TOP_CON5,
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.agent_disable_shift = 4,
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.ch_num_reg = -1,
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.ch_num_shift = 0,
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.ch_num_maskbit = 0,
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.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
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.msb_shift = 4,
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.msb2_reg = AFE_NORMAL_END_ADR_MSB,
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.msb2_shift = 4,
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}
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};
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struct mt8195_afe_rate {
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unsigned int rate;
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unsigned int reg_value;
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};
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static const struct mt8195_afe_rate mt8195_afe_rates[] = {
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{
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.rate = 8000,
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.reg_value = 0,
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},
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{
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.rate = 12000,
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.reg_value = 1,
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},
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{
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.rate = 16000,
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.reg_value = 2,
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},
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{
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.rate = 24000,
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.reg_value = 3,
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},
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{
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.rate = 32000,
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.reg_value = 4,
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},
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{
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.rate = 48000,
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.reg_value = 5,
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},
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{
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.rate = 96000,
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.reg_value = 6,
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},
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{
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.rate = 192000,
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.reg_value = 7,
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},
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{
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.rate = 384000,
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.reg_value = 8,
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},
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{
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.rate = 7350,
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.reg_value = 16,
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},
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{
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.rate = 11025,
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.reg_value = 17,
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},
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{
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.rate = 14700,
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.reg_value = 18,
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},
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{
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.rate = 22050,
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.reg_value = 19,
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},
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{
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.rate = 29400,
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.reg_value = 20,
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},
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{
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.rate = 44100,
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.reg_value = 21,
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},
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{
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.rate = 88200,
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.reg_value = 22,
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},
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{
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.rate = 176400,
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.reg_value = 23,
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},
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{
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.rate = 352800,
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.reg_value = 24,
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},
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};
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static unsigned int mt8195_afe_fs_timing(unsigned int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++)
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if (mt8195_afe_rates[i].rate == rate)
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return mt8195_afe_rates[i].reg_value;
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return -EINVAL;
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}
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static unsigned int mt8195_afe_fs(unsigned int rate, int aud_blk)
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{
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return mt8195_afe_fs_timing(rate);
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}
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static unsigned int mt8195_afe2adsp_addr(unsigned int addr)
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{
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/*TODO : Need apply the address remap */
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return addr;
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}
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static unsigned int mt8195_adsp2afe_addr(unsigned int addr)
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{
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/* TODO : Need apply the address remap */
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return addr;
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}
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struct mtk_base_afe_platform mtk_afe_platform = {
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.base_addr = AFE_BASE_ADDR,
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.memif_datas = memif_data,
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.memif_size = MT8195_MEMIF_NUM,
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.memif_dl_num = MT8195_MEMIF_DL_NUM,
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.memif_32bit_supported = 0,
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.irq_datas = NULL,
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.irqs_size = 0,
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.dais_size = MT8195_DAI_NUM,
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.afe2adsp_addr = mt8195_afe2adsp_addr,
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.adsp2afe_addr = mt8195_adsp2afe_addr,
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.afe_fs = mt8195_afe_fs,
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.irq_fs = mt8195_afe_fs_timing,
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};
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@ -0,0 +1,68 @@
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: YC Hung <yc.hung@mediatek.com>
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#ifndef _MT_8195_AFE_COMMON_H_
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#define _MT_8195_AFE_COMMON_H_
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/* AFE: the abbreviation for Audio Front End */
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enum {
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MT8195_MEMIF_START,
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MT8195_MEMIF_DL_START = MT8195_MEMIF_START,
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MT8195_MEMIF_DL2 = MT8195_MEMIF_DL_START,
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MT8195_MEMIF_DL3,
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MT8195_MEMIF_DL_END,
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MT8195_MEMIF_UL_START = MT8195_MEMIF_DL_END,
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MT8195_MEMIF_UL4 = MT8195_MEMIF_UL_START,
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MT8195_MEMIF_UL5,
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MT8195_MEMIF_UL_END,
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MT8195_MEMIF_END = MT8195_MEMIF_UL_END,
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MT8195_MEMIF_DL_NUM = (MT8195_MEMIF_DL_END - MT8195_MEMIF_DL_START),
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MT8195_MEMIF_UL_NUM = (MT8195_MEMIF_UL_END - MT8195_MEMIF_UL_START),
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MT8195_MEMIF_NUM = (MT8195_MEMIF_END - MT8195_MEMIF_START),
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};
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enum {
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MT8195_IRQ_0,
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MT8195_IRQ_1,
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MT8195_IRQ_2,
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MT8195_IRQ_3,
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MT8195_IRQ_4,
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MT8195_IRQ_5,
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MT8195_IRQ_6,
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MT8195_IRQ_7,
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MT8195_IRQ_8,
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MT8195_IRQ_9,
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MT8195_IRQ_10,
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MT8195_IRQ_11,
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MT8195_IRQ_12,
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MT8195_IRQ_13,
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MT8195_IRQ_14,
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MT8195_IRQ_15,
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MT8195_IRQ_16,
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MT8195_IRQ_17,
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MT8195_IRQ_18,
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MT8195_IRQ_19,
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MT8195_IRQ_20,
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MT8195_IRQ_21,
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MT8195_IRQ_22,
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MT8195_IRQ_23,
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MT8195_IRQ_24,
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MT8195_IRQ_25,
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MT8195_IRQ_26,
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MT8195_IRQ_31, /* used only for TDM */
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MT8195_IRQ_NUM,
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};
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enum {
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MT8195_AFE_IO_ETDM2_OUT,
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MT8195_AFE_IO_ETDM1_OUT,
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MT8195_AFE_IO_UL_SRC1,
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MT8195_AFE_IO_ETDM2_IN,
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MT8195_DAI_NUM,
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};
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#endif
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