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topology: sof-glk-cs42l42: using 2.4MHz bclk 

By changing bclk to 2.4MHz, we can use XTAL as clock source and reduce
power consumption.

Signed-off-by: Brent Lu <brent.lu@intel.com>
This commit is contained in:
Brent Lu 2021-06-08 17:55:05 +08:00 committed by Liam Girdwood
parent b634aebad7
commit 5abd8a9ea5
1 changed files with 2 additions and 2 deletions
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4
tools/topology/sof-glk-da7219.m4
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@ -182,9 +182,9 @@ DAI_CONFIG(SSP, 2, 1, SSP2-Codec,
#SSP 2 (ID: 1) with 19.2 MHz mclk with MCLK_ID 1 (unused), 3.072 MHz bclk, no quirk, 10 ms BCLK delay
DAI_CONFIG(SSP, 2, 1, SSP2-Codec,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in),
SSP_CLOCK(bclk, 3072000, codec_slave),
SSP_CLOCK(bclk, 2400000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
SSP_TDM(2, 25, 3, 3),
SSP_CONFIG_DATA(SSP, 2, 16, 1, 0, 10)))
', )