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zephyr: include: rtos: Switch to using Zephyr cache management API 

Thanks to PR [1], Zephyr cache management API can now be
used on xtensa-based SoCs. As a consequence to this, there's
no longer a need to use SOF's arch/ layer for cache management.
This commit forces all SoCs which support Zephyr to use
its native cache management API.

[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2023-04-07 17:08:35 +03:00 committed by Kai Vehmanen
parent 601d2bc41e
commit 58b96d1c7f
1 changed files with 53 additions and 2 deletions
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55
zephyr/include/rtos/cache.h
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@ -6,9 +6,23 @@
#ifndef __ZEPHYR_RTOS_CACHE_H__
#define __ZEPHYR_RTOS_CACHE_H__
/* TODO: align with Zephyr generic cache API when ready */
#define __SOF_LIB_CACHE_H__
#include <arch/lib/cache.h>
#if !defined(__ASSEMBLER__) && !defined(LINKER)
#include <zephyr/cache.h>
#include <zephyr/debug/sparse.h>
#if defined(CONFIG_XTENSA) && defined(CONFIG_INTEL)
/* definitions required by xtensa-based Intel platforms.
*
* TODO: if possible, move these to Zephyr.
*/
#define SRAM_UNCACHED_ALIAS 0x20000000
#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
#endif /* defined(CONFIG_XTENSA) && defined(CONFIG_INTEL) */
/* writeback and invalidate data */
#define CACHE_WRITEBACK_INV 0
@ -16,4 +30,41 @@
/* invalidate data */
#define CACHE_INVALIDATE 1
/* sanity check - make sure CONFIG_DCACHE_LINE_SIZE is valid */
#if !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0)
#define DCACHE_LINE_SIZE CONFIG_DCACHE_LINE_SIZE
#else
#if defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX)
#define DCACHE_LINE_SIZE 64
#else
#error "Invalid cache configuration."
#endif /* defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX) */
#endif /* !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0) */
static inline void dcache_writeback_region(void __sparse_cache *addr, size_t size)
{
/* TODO: return value should probably be checked here */
sys_cache_data_flush_range((__sparse_force void *)addr, size);
}
static inline void dcache_invalidate_region(void __sparse_cache *addr, size_t size)
{
/* TODO: return value should probably be checked here */
sys_cache_data_invd_range((__sparse_force void *)addr, size);
}
static inline void icache_invalidate_region(void __sparse_cache *addr, size_t size)
{
/* TODO: return value should probably be checked here */
sys_cache_instr_invd_range((__sparse_force void *)addr, size);
}
static inline void dcache_writeback_invalidate_region(void __sparse_cache *addr, size_t size)
{
/* TODO: return value should probably be checked here */
sys_cache_data_flush_and_invd_range((__sparse_force void *)addr, size);
}
#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
#endif /* __ZEPHYR_RTOS_CACHE_H__ */