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mailbox: use mailbox function for SW_REG 

SW_REG is in memory window and the cache is enabled, need to
writeback the SW_REG.

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
This commit is contained in:
Pan Xiuli 2018-05-04 15:41:48 +08:00 committed by Liam Girdwood
parent 85ae8e7418
commit 530ef2a213
3 changed files with 22 additions and 4 deletions
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14
src/include/sof/mailbox.h
View File

@ -26,6 +26,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/ */
#ifndef __INCLUDE_MAILBOX__ #ifndef __INCLUDE_MAILBOX__
@ -36,6 +37,11 @@
#include <stdint.h> #include <stdint.h>
#include <sof/string.h> #include <sof/string.h>
/* For those platform did not have SW_REG window, use DEBUG at now */
#ifndef MAILBOX_SW_REG_BASE
#define MAILBOX_SW_REG_BASE MAILBOX_DEBUG_BASE
#endif /* MAILBOX_SW_REG_BASE */
/* 4k should be enough for everyone ..... */ /* 4k should be enough for everyone ..... */
#define IPC_MAX_MAILBOX_BYTES 0x1000 #define IPC_MAX_MAILBOX_BYTES 0x1000
@ -100,4 +106,12 @@ void mailbox_stream_write(size_t offset, const void *src, size_t bytes)
bytes); bytes);
} }
static inline
void mailbox_sw_reg_write(size_t offset, uint32_t src)
{
*((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src;
dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset),
sizeof(src));
}
#endif #endif

6
src/platform/apollolake/include/platform/platform.h
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@ -27,6 +27,7 @@
* *
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com> * Keyon Jie <yang.jie@linux.intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/ */
#ifndef __PLATFORM_PLATFORM_H__ #ifndef __PLATFORM_PLATFORM_H__
@ -117,13 +118,14 @@ struct sof;
/* Platform defined panic code */ /* Platform defined panic code */
#define platform_panic(__x) { \ #define platform_panic(__x) { \
sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
(0xdead000 | (__x)) & 0x3fffffff); \
ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ ipc_write(IPC_DIPCI, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \
} }
/* Platform defined trace code */ /* Platform defined trace code */
#define platform_trace_point(__x) \ #define platform_trace_point(__x) \
sw_reg_write(SRAM_REG_FW_TRACEP, __x) mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
extern struct timer *platform_timer; extern struct timer *platform_timer;

6
src/platform/cannonlake/include/platform/platform.h
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@ -28,6 +28,7 @@
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com> * Keyon Jie <yang.jie@linux.intel.com>
* Rander Wang <rander.wang@intel.com> * Rander Wang <rander.wang@intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/ */
#ifndef __PLATFORM_PLATFORM_H__ #ifndef __PLATFORM_PLATFORM_H__
@ -112,13 +113,14 @@ struct sof;
/* Platform defined trace code */ /* Platform defined trace code */
#define platform_panic(__x) { \ #define platform_panic(__x) { \
sw_reg_write(SRAM_REG_FW_STATUS, (0xdead000 | __x) & 0x3fffffff); \ mailbox_sw_reg_write(SRAM_REG_FW_STATUS, \
(0xdead000 | (__x)) & 0x3fffffff); \
ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \ ipc_write(IPC_DIPCIDR, 0x80000000 | ((0xdead000 | __x) & 0x3fffffff)); \
} }
/* Platform defined trace code */ /* Platform defined trace code */
#define platform_trace_point(__x) \ #define platform_trace_point(__x) \
sw_reg_write(SRAM_REG_FW_TRACEP, __x) mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
extern struct timer *platform_timer; extern struct timer *platform_timer;