mirror of https://github.com/thesofproject/sof.git
platform: mtk: add afe-platform support for mt8186
Add memif data for AFE Add common and regs header for AFE Add AFE platform for mt8186 audio/dsp AFE: the abbreviation for Audio Front End Signed-off-by: Chunxu Li <chunxu.li@mediatek.com>
This commit is contained in:
Chunxu Li
Curtis Malainey
parent
ad0d4fb3f8
commit
529b1d0cc2
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2022 Mediatek
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//
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// Author: Chunxu Li <chunxu.li@mediatek.com>
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#include <sof/common.h>
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#include <errno.h>
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#include <sof/drivers/afe-drv.h>
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#include <mt8186-afe-regs.h>
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#include <mt8186-afe-common.h>
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/*
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* AFE: Audio Front-End
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*
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* frontend (memif):
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* memory interface
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* UL (uplink for capture)
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* DL (downlink for playback)
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* backend:
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* TDM In
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* TMD Out
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* DMIC
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* GASRC
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* I2S Out
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* I2S In
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* etc.
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* interconn:
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* inter-connection,
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* connect frontends and backends as DSP path
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*/
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static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = {
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[MT8186_MEMIF_DL1] = {
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.name = "DL1",
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.id = MT8186_MEMIF_DL1,
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.reg_ofs_base = AFE_DL1_BASE,
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.reg_ofs_cur = AFE_DL1_CUR,
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.reg_ofs_end = AFE_DL1_END,
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.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
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.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
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.reg_ofs_end_msb = AFE_DL1_END_MSB,
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.fs_reg = AFE_DL1_CON0,
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.fs_shift = DL1_MODE_SFT,
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.fs_maskbit = DL1_MODE_MASK,
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.mono_reg = AFE_DL1_CON0,
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.mono_shift = DL1_MONO_SFT,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = DL1_ON_SFT,
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.hd_reg = AFE_DL1_CON0,
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.hd_shift = DL1_HD_MODE_SFT,
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.hd_align_reg = AFE_DL1_CON0,
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.hd_align_mshift = DL1_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.ch_num_reg = -1,
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.ch_num_shift = -1,
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.ch_num_maskbit = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.msb2_reg = -1,
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.msb2_shift = -1,
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.pbuf_reg = AFE_DL1_CON0,
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.pbuf_mask = DL1_PBUF_SIZE_MASK,
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.pbuf_shift = DL1_PBUF_SIZE_SFT,
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.minlen_reg = AFE_DL1_CON0,
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.minlen_mask = DL1_MINLEN_MASK,
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.minlen_shift = DL1_MINLEN_SFT,
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},
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[MT8186_MEMIF_DL2] = {
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.name = "DL2",
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.id = MT8186_MEMIF_DL2,
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.reg_ofs_base = AFE_DL2_BASE,
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.reg_ofs_cur = AFE_DL2_CUR,
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.reg_ofs_end = AFE_DL2_END,
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.reg_ofs_base_msb = AFE_DL2_BASE_MSB,
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.reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
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.reg_ofs_end_msb = AFE_DL2_END_MSB,
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.fs_reg = AFE_DL2_CON0,
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.fs_shift = DL2_MODE_SFT,
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.fs_maskbit = DL2_MODE_MASK,
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.mono_reg = AFE_DL2_CON0,
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.mono_shift = DL2_MONO_SFT,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = DL2_ON_SFT,
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.hd_reg = AFE_DL2_CON0,
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.hd_shift = DL2_HD_MODE_SFT,
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.hd_align_reg = AFE_DL2_CON0,
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.hd_align_mshift = DL2_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.ch_num_reg = -1,
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.ch_num_shift = -1,
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.ch_num_maskbit = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.msb2_reg = -1,
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.msb2_shift = -1,
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.pbuf_reg = AFE_DL2_CON0,
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.pbuf_mask = DL2_PBUF_SIZE_MASK,
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.pbuf_shift = DL2_PBUF_SIZE_SFT,
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.minlen_reg = AFE_DL2_CON0,
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.minlen_mask = DL2_MINLEN_MASK,
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.minlen_shift = DL2_MINLEN_SFT,
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},
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[MT8186_MEMIF_UL1] = {
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.name = "UL1",
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.id = MT8186_MEMIF_UL1,
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.reg_ofs_base = AFE_VUL12_BASE,
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.reg_ofs_cur = AFE_VUL12_CUR,
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.reg_ofs_end = AFE_VUL12_END,
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.reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
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.reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
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.reg_ofs_end_msb = AFE_VUL12_END_MSB,
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.fs_reg = AFE_VUL12_CON0,
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.fs_shift = VUL12_MODE_SFT,
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.fs_maskbit = VUL12_MODE_MASK,
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.mono_reg = AFE_VUL12_CON0,
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.mono_shift = VUL12_MONO_SFT,
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.quad_ch_reg = AFE_VUL12_CON0,
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.quad_ch_mask = VUL12_4CH_EN_MASK,
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.quad_ch_shift = VUL12_4CH_EN_SFT,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = VUL12_ON_SFT,
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.hd_reg = AFE_VUL12_CON0,
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.hd_shift = VUL12_HD_MODE_SFT,
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.hd_align_reg = AFE_VUL12_CON0,
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.hd_align_mshift = VUL12_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.ch_num_reg = -1,
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.ch_num_shift = -1,
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.ch_num_maskbit = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.msb2_reg = -1,
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.msb2_shift = -1,
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},
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[MT8186_MEMIF_UL2] = {
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.name = "UL2",
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.id = MT8186_MEMIF_UL2,
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.reg_ofs_base = AFE_AWB_BASE,
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.reg_ofs_cur = AFE_AWB_CUR,
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.reg_ofs_end = AFE_AWB_END,
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.reg_ofs_base_msb = AFE_AWB_BASE_MSB,
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.reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
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.reg_ofs_end_msb = AFE_AWB_END_MSB,
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.fs_reg = AFE_AWB_CON0,
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.fs_shift = AWB_MODE_SFT,
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.fs_maskbit = AWB_MODE_MASK,
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.mono_reg = AFE_AWB_CON0,
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.mono_shift = AWB_MONO_SFT,
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.enable_reg = AFE_DAC_CON0,
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.enable_shift = AWB_ON_SFT,
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.hd_reg = AFE_AWB_CON0,
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.hd_shift = AWB_HD_MODE_SFT,
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.hd_align_reg = AFE_AWB_CON0,
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.hd_align_mshift = AWB_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.ch_num_reg = -1,
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.ch_num_shift = -1,
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.ch_num_maskbit = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.msb2_reg = -1,
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.msb2_shift = -1,
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}
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};
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struct mt8186_afe_rate {
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unsigned int rate;
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unsigned int reg_value;
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};
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enum {
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MTK_AFE_RATE_8K = 0,
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MTK_AFE_RATE_11K = 1,
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MTK_AFE_RATE_12K = 2,
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MTK_AFE_RATE_384K = 3,
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MTK_AFE_RATE_16K = 4,
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MTK_AFE_RATE_22K = 5,
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MTK_AFE_RATE_24K = 6,
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MTK_AFE_RATE_352K = 7,
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MTK_AFE_RATE_32K = 8,
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MTK_AFE_RATE_44K = 9,
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MTK_AFE_RATE_48K = 10,
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MTK_AFE_RATE_88K = 11,
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MTK_AFE_RATE_96K = 12,
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MTK_AFE_RATE_176K = 13,
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MTK_AFE_RATE_192K = 14,
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MTK_AFE_RATE_260K = 15,
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};
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static const struct mt8186_afe_rate mt8186_afe_rates[] = {
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{
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.rate = 8000,
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.reg_value = MTK_AFE_RATE_8K,
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},
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{
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.rate = 12000,
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.reg_value = MTK_AFE_RATE_12K,
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},
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{
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.rate = 16000,
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.reg_value = MTK_AFE_RATE_16K,
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},
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{
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.rate = 24000,
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.reg_value = MTK_AFE_RATE_24K,
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},
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{
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.rate = 32000,
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.reg_value = MTK_AFE_RATE_32K,
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},
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{
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.rate = 48000,
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.reg_value = MTK_AFE_RATE_48K,
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},
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{
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.rate = 96000,
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.reg_value = MTK_AFE_RATE_96K,
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},
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{
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.rate = 192000,
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.reg_value = MTK_AFE_RATE_192K,
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},
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{
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.rate = 384000,
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.reg_value = MTK_AFE_RATE_384K,
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},
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{
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.rate = 11025,
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.reg_value = MTK_AFE_RATE_11K,
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},
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{
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.rate = 22050,
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.reg_value = MTK_AFE_RATE_22K,
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},
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{
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.rate = 44100,
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.reg_value = MTK_AFE_RATE_44K,
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},
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{
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.rate = 88200,
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.reg_value = MTK_AFE_RATE_88K,
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},
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{
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.rate = 176400,
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.reg_value = MTK_AFE_RATE_176K,
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},
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{
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.rate = 352800,
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.reg_value = MTK_AFE_RATE_352K,
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},
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};
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static unsigned int mt8186_afe_fs_timing(unsigned int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mt8186_afe_rates); i++)
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if (mt8186_afe_rates[i].rate == rate)
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return mt8186_afe_rates[i].reg_value;
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return -EINVAL;
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}
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static unsigned int mt8186_afe_fs(unsigned int rate, int aud_blk)
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{
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return mt8186_afe_fs_timing(rate);
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}
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static unsigned int mt8186_afe2adsp_addr(unsigned int addr)
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{
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/*TODO : Need apply the address remap */
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return addr;
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}
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static unsigned int mt8186_adsp2afe_addr(unsigned int addr)
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{
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/* TODO : Need apply the address remap */
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return addr;
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}
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struct mtk_base_afe_platform mtk_afe_platform = {
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.base_addr = AFE_BASE_ADDR,
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.memif_datas = memif_data,
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.memif_size = MT8186_MEMIF_NUM,
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.memif_dl_num = MT8186_MEMIF_DL_NUM,
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.memif_32bit_supported = 0,
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.irq_datas = NULL,
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.irqs_size = 0,
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.dais_size = MT8186_DAI_NUM,
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.afe2adsp_addr = mt8186_afe2adsp_addr,
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.adsp2afe_addr = mt8186_adsp2afe_addr,
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.afe_fs = mt8186_afe_fs,
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.irq_fs = mt8186_afe_fs_timing,
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};
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@ -0,0 +1,67 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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//
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// Copyright(c) 2022 Mediatek
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//
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// Author: Chunxu Li <chunxu.li@mediatek.com>
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#ifndef _MT_8186_AFE_COMMON_H_
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#define _MT_8186_AFE_COMMON_H_
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/* AFE: the abbreviation for Audio Front End */
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enum {
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MT8186_MEMIF_START,
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MT8186_MEMIF_DL_START = MT8186_MEMIF_START,
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MT8186_MEMIF_DL1 = MT8186_MEMIF_DL_START,
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MT8186_MEMIF_DL2,
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MT8186_MEMIF_DL_END,
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MT8186_MEMIF_UL_START = MT8186_MEMIF_DL_END,
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MT8186_MEMIF_UL1 = MT8186_MEMIF_UL_START,
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MT8186_MEMIF_UL2,
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MT8186_MEMIF_UL_END,
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MT8186_MEMIF_END = MT8186_MEMIF_UL_END,
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MT8186_MEMIF_DL_NUM = (MT8186_MEMIF_DL_END - MT8186_MEMIF_DL_START),
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MT8186_MEMIF_UL_NUM = (MT8186_MEMIF_UL_END - MT8186_MEMIF_UL_START),
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MT8186_MEMIF_NUM = (MT8186_MEMIF_END - MT8186_MEMIF_START),
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};
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enum {
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MT8186_IRQ_0,
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MT8186_IRQ_1,
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MT8186_IRQ_2,
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MT8186_IRQ_3,
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MT8186_IRQ_4,
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MT8186_IRQ_5,
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MT8186_IRQ_6,
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MT8186_IRQ_7,
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MT8186_IRQ_8,
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MT8186_IRQ_9,
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MT8186_IRQ_10,
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MT8186_IRQ_11,
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MT8186_IRQ_12,
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MT8186_IRQ_13,
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MT8186_IRQ_14,
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MT8186_IRQ_15,
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MT8186_IRQ_16,
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MT8186_IRQ_17,
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MT8186_IRQ_18,
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MT8186_IRQ_19,
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MT8186_IRQ_20,
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MT8186_IRQ_21,
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MT8186_IRQ_22,
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MT8186_IRQ_23,
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MT8186_IRQ_24,
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MT8186_IRQ_25,
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MT8186_IRQ_26,
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MT8186_IRQ_NUM,
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};
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enum {
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MT8186_AFE_IO_I2S1,
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MT8186_AFE_IO_I2S3,
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MT8186_AFE_IO_UL_SRC1,
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MT8186_AFE_IO_I2S0,
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MT8186_DAI_NUM,
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};
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#endif
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