pipeline: move static scheduling params to static_pipeline.c

Move all the static scheduling params out of the platform headers and into
the static pipeline source as they are no longer used by dynamic pipeline
code.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood 2017-08-10 16:30:11 +01:00
parent fb1d0047e2
commit 4d0e197e07
5 changed files with 18 additions and 19 deletions

View File

@ -146,7 +146,7 @@ static void dai_dma_cb(void *data, uint32_t type, struct dma_sg_elem *next)
}
/* notify pipeline that DAI needs it's buffer processed */
pipeline_schedule_copy(dev->pipeline, dev, PLAT_DAI_SCHED, TASK_PRI_HIGH);
pipeline_schedule_copy(dev->pipeline, dev);
next_copy:

View File

@ -703,10 +703,10 @@ static int pipeline_copy_to_downstream(struct comp_dev *start,
}
/* notify pipeline that this component requires buffers emptied/filled */
void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev,
uint32_t deadline, uint32_t priority)
void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev)
{
schedule_task(&p->pipe_task, deadline, priority, dev);
schedule_task(&p->pipe_task, p->ipc_pipe.deadline,
p->ipc_pipe.priority, dev);
schedule();
}

View File

@ -53,6 +53,19 @@
/* 2 * 24 (32) bit*/
#define PLATFORM_DAI_FRAME_SIZE 8
/* Platform Host DMA buffer config - these should align with DMA engine */
#define PLAT_HOST_PERIOD_FRAMES 48 /* must be multiple of DMA burst size */
#define PLAT_HOST_PERIODS 2 /* give enough latency for DMA refill */
/* Platform Dev DMA buffer config - these should align with DMA engine */
#define PLAT_DAI_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
#define PLAT_DAI_PERIODS 2 /* give enough latency for DMA refill */
#define PLAT_DAI_SCHED 1000 /* scheduling time in usecs */
/* Platform internal buffer config - these should align with DMA engine */
#define PLAT_INT_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
#define PLAT_INT_PERIODS 2 /* give enough latency for DMA refill */
/*
* Static Buffer Convenience Constructors.
*/

View File

@ -108,8 +108,7 @@ int init_static_pipeline(struct ipc *ipc);
/* pipeline creation */
int init_pipeline(void);
void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev,
uint32_t deadline, uint32_t priority);
void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev);
void pipeline_schedule(void *arg);

View File

@ -67,19 +67,6 @@ struct reef;
#define PLATFORM_MAX_CHANNELS 4
#define PLATFORM_MAX_STREAMS 5
/* Platform Host DMA buffer config - these should align with DMA engine */
#define PLAT_HOST_PERIOD_FRAMES 48 /* must be multiple of DMA burst size */
#define PLAT_HOST_PERIODS 2 /* give enough latency for DMA refill */
/* Platform Dev DMA buffer config - these should align with DMA engine */
#define PLAT_DAI_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
#define PLAT_DAI_PERIODS 2 /* give enough latency for DMA refill */
#define PLAT_DAI_SCHED 1000 /* scheduling time in usecs */
/* Platform internal buffer config - these should align with DMA engine */
#define PLAT_INT_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
#define PLAT_INT_PERIODS 2 /* give enough latency for DMA refill */
#define PLATFORM_SCHED_CLOCK CLK_SSP
#define PLATFORM_NUM_MMAP_POSN 10