mirror of https://github.com/thesofproject/sof.git
pipeline: move static scheduling params to static_pipeline.c
Move all the static scheduling params out of the platform headers and into the static pipeline source as they are no longer used by dynamic pipeline code. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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@ -146,7 +146,7 @@ static void dai_dma_cb(void *data, uint32_t type, struct dma_sg_elem *next)
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}
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/* notify pipeline that DAI needs it's buffer processed */
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pipeline_schedule_copy(dev->pipeline, dev, PLAT_DAI_SCHED, TASK_PRI_HIGH);
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pipeline_schedule_copy(dev->pipeline, dev);
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next_copy:
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@ -703,10 +703,10 @@ static int pipeline_copy_to_downstream(struct comp_dev *start,
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}
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/* notify pipeline that this component requires buffers emptied/filled */
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void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev,
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uint32_t deadline, uint32_t priority)
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void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev)
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{
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schedule_task(&p->pipe_task, deadline, priority, dev);
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schedule_task(&p->pipe_task, p->ipc_pipe.deadline,
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p->ipc_pipe.priority, dev);
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schedule();
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}
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@ -53,6 +53,19 @@
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/* 2 * 24 (32) bit*/
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#define PLATFORM_DAI_FRAME_SIZE 8
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/* Platform Host DMA buffer config - these should align with DMA engine */
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#define PLAT_HOST_PERIOD_FRAMES 48 /* must be multiple of DMA burst size */
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#define PLAT_HOST_PERIODS 2 /* give enough latency for DMA refill */
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/* Platform Dev DMA buffer config - these should align with DMA engine */
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#define PLAT_DAI_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
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#define PLAT_DAI_PERIODS 2 /* give enough latency for DMA refill */
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#define PLAT_DAI_SCHED 1000 /* scheduling time in usecs */
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/* Platform internal buffer config - these should align with DMA engine */
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#define PLAT_INT_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
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#define PLAT_INT_PERIODS 2 /* give enough latency for DMA refill */
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/*
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* Static Buffer Convenience Constructors.
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*/
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@ -108,8 +108,7 @@ int init_static_pipeline(struct ipc *ipc);
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/* pipeline creation */
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int init_pipeline(void);
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void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev,
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uint32_t deadline, uint32_t priority);
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void pipeline_schedule_copy(struct pipeline *p, struct comp_dev *dev);
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void pipeline_schedule(void *arg);
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@ -67,19 +67,6 @@ struct reef;
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#define PLATFORM_MAX_CHANNELS 4
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#define PLATFORM_MAX_STREAMS 5
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/* Platform Host DMA buffer config - these should align with DMA engine */
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#define PLAT_HOST_PERIOD_FRAMES 48 /* must be multiple of DMA burst size */
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#define PLAT_HOST_PERIODS 2 /* give enough latency for DMA refill */
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/* Platform Dev DMA buffer config - these should align with DMA engine */
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#define PLAT_DAI_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
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#define PLAT_DAI_PERIODS 2 /* give enough latency for DMA refill */
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#define PLAT_DAI_SCHED 1000 /* scheduling time in usecs */
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/* Platform internal buffer config - these should align with DMA engine */
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#define PLAT_INT_PERIOD_FRAMES 48 /* must be multiple of DMA+DEV burst size */
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#define PLAT_INT_PERIODS 2 /* give enough latency for DMA refill */
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#define PLATFORM_SCHED_CLOCK CLK_SSP
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#define PLATFORM_NUM_MMAP_POSN 10
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