mirror of https://github.com/thesofproject/sof.git
Merge pull request #561 from lbetlej/cnl_pg_sram_on_d3
Added SRAM power gating on D3 entry for cAVS 1.8 (i.e. Cannonlake).
This commit is contained in:
commit
4c8deb72a3
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@ -50,8 +50,14 @@
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#include <platform/platform.h>
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#include <sof/audio/component.h>
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#include <sof/audio/pipeline.h>
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//<<<<<<< HEAD
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#include <uapi/ipc/header.h>
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//=======
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//#include <uapi/ipc.h>
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//#include <sof/intel-ipc.h>
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#include <platform/pm_runtime.h>
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//>>>>>>> Added SRAM power gating on D3 entry for cAVS 1.8 (i.e. Cannonlake).
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extern struct ipc *_ipc;
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/* test code to check working IRQ */
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@ -139,8 +145,14 @@ done:
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// TODO: signal audio work to enter D3 in normal context
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/* are we about to enter D3 ? */
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if (iipc->pm_prepare_D3) {
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while (1)
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wait_for_interrupt(0);
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#if defined(CONFIG_CANNONLAKE)
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/* no return - memory will be powered off */
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platform_pm_runtime_power_off();
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#else
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//TODO: add support for Icelake, consider a spearate file icl-ipc.c
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while (1)
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wait_for_interrupt(0);
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#endif
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}
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tracev_ipc("CmD");
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@ -8,7 +8,7 @@ noinst_LTLIBRARIES = libplatform.la
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libplatform_la_LIBADD = ../intel/cavs/libcavsplatform.la
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libplatform_la_SOURCES =
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libplatform_la_SOURCES = power_down.S
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libplatform_la_CFLAGS = \
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$(AM_CFLAGS) \
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@ -17,6 +17,12 @@ libplatform_la_CFLAGS = \
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$(PLATFORM_INCDIR) \
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$(SOF_INCDIR)
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libplatform_la_CCASFLAGS = \
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$(ARCH_INCDIR) \
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$(ASFLAGS) \
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$(ARCH_ASFLAGS) \
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$(PLATFORM_INCDIR)
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noinst_PROGRAMS = module boot_module
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module_SOURCES = \
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@ -10,4 +10,6 @@ noinst_HEADERS = \
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platform.h \
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pm_runtime.h \
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shim.h \
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timer.h
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timer.h \
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asm_memory_management.h \
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power_down.h
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@ -0,0 +1,112 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lech Betlej <lech.betlej@linux.intel.com>
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*/
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/**
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* \file platform/cannonlake/include/platform/asm_memory_management.h
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* \brief Macros for power gating memory banks specific for cAVS 1.8
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* \(CannonLake)
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* \author Lech Betlej <lech.betlej@linux.intel.com>
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*/
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#ifndef ASM_MEMORY_MANAGEMENT_H
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#define ASM_MEMORY_MANAGEMENT_H
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#ifndef ASSEMBLY
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#warning "ASSEMBLY macro not defined. Header can't be inluded in C files"
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#warning "The file is intended to be includded in assembly files only."
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#endif
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#include <platform/shim.h>
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#include <platform/platcfg.h>
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#define MAX_EBB_BANKS_IN_SEGMENT 32
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#define HPSRAM_MASK(seg_idx)\
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((1 << (PLATFORM_HPSRAM_EBB_COUNT\
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- MAX_EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
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#define LPSRAM_MASK ((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1)
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#define MAX_MEMORY_SEGMENTS ((PLATFORM_HPSRAM_EBB_COUNT + \
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MAX_EBB_BANKS_IN_SEGMENT - 1) / MAX_EBB_BANKS_IN_SEGMENT)
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/**
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* powers down entire hpsram. on entry lirerals and code for section from
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* where this code is executed needs to be placed in memory which is not
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* HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or
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* L1 SRAM)
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*/
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.macro m_cavs_hpsram_power_down_entire ax, ay, az
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//TODO: add LDO control
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// SEGMENT #0
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movi \az, SHIM_HSPGCTL(0)
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movi \ax, SHIM_HSPGISTS(0)
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movi \ay, HPSRAM_MASK(0)
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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// SEGMENT #1
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movi \az, SHIM_HSPGCTL(1)
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movi \ax, SHIM_HSPGISTS(1)
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movi \ay, HPSRAM_MASK(1)
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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// TODO: Add LDO control
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.endm
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.macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
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// TODO: Add LDO Control
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movi \ax, SHIM_HSPGCTL(\segment_index)
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movi \ay, SHIM_HSPGISTS(\segment_index)
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s32i \mask, \ax, 0
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memw
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// assumed that HDA shared dma buffer will be in LPSRAM
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1 :
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l32i \ax, \ay, 0
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bne \ax, \mask, 1b
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// TODO: Add LDO Control
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.endm
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.macro m_cavs_lpsram_power_down_entire ax, ay, az
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movi \az, LSPGISTS
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movi \ax, LSPGCTL
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movi \ay, LPSRAM_MASK
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s32i \ay, \ax, 0
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memw
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// assumed that HDA shared dma buffer will be in LPSRAM
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movi \ax, 4096
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1 :
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addi \ax, \ax, -1
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bnez \ax, 1b
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.endm
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#endif /* ASM_MEMORY_MANAGEMENT_H */
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@ -35,6 +35,12 @@
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#define PLATFORM_CORE_COUNT 4
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#define PLATFORM_LPSRAM_EBB_COUNT 1
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#define PLATFORM_HPSRAM_EBB_COUNT 47
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#define PLATFORM_HPSRAM_SEGMENTS 2
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#define PLATFORM_MASTER_CORE_ID 0
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#endif
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@ -70,4 +70,9 @@ void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index,
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void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index,
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uint32_t flags);
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/**
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* \brief Power gates platform specific hardware resources.
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*/
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void platform_pm_runtime_power_off(void);
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#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
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@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
|
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* names of its contributors may be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lech Betlej <lech.betlej@linux.intel.com>
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*/
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#ifndef CANNONLAKE_INCLUDE_PLATFORM_POWER_DOWN_H
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#define CANNONLAKE_INCLUDE_PLATFORM_POWER_DOWN_H
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#include <stdbool.h>
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/**
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* Power down procedure.
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* Locks its code in L1 cache and shuts down memories.
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* @param disable_lpsram flag if LPSRAM is to be disabled (whole)
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* @param hpsram_pwrgating_mask pointer to memory segments power gating mask
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* (each bit corresponds to one ebb)
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* @return nothing returned - this function never quits
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*/
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void power_down(bool disable_lpsram, uint32_t *hpsram_pwrgating_mask);
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#endif /* CANNONLAKE_INCLUDE_PLATFORM_POWER_DOWN_H */
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@ -196,6 +196,9 @@
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#define HSRMCTL1 0x71D24
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#define HSPGISTS1 0x71D28
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#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
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#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x18 * (x))
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#define LSPGCTL 0x71D50
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#define LSRMCTL 0x71D54
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#define LSPGISTS 0x71D58
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@ -0,0 +1,140 @@
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/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
|
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lech Betlej <lech.betlej@linux.intel.com>
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*/
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/**
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* \file platform/apollolake/power_down.S
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* \brief Power gating memory banks - implementation specific for Apollolake
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* \author Lech Betlej <lech.betlej@linux.intel.com>
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*/
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#include <platform/asm_memory_management.h>
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.section .text, "ax"
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.align 64
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literals:
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.literal_position
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.global power_down
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.type power_down, @function
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/**
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* Perform power down.
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*
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* Depending on arguments, memories are switched off.
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* A2 - argument for LPSRAM
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* A3 - pointer to array containing power gating mask.
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*Size of array is determined by MEMORY_SEGMENTS define.
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* A4 - platform type
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* A5 - response_to_ipc
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*/
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//TODO: add IPC reply sending before core enters waiti
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#define b_enable_lpsram a2
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#define pu32_hpsram_mask a3
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#define temp_reg0 a6
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#define temp_reg1 a7
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#define temp_reg2 a8
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#define temp_reg3 a9
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#define pfl_reg a15
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power_down:
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entry sp, 32
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// effectively executes:
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// xthal_dcache_region_lock(&literals, 128);
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// xthal_dcache_region_lock(&powerdown, 256);
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// xthal_dcache_region_lock(&pu32_hpsram_mask, 64);
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movi pfl_reg, literals
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dpfl pfl_reg, 0
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dpfl pfl_reg, 64
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movi pfl_reg, power_down
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ipfl pfl_reg, 0
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ipfl pfl_reg, 64
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ipfl pfl_reg, 128
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ipfl pfl_reg, 192
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mov pfl_reg, pu32_hpsram_mask
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dpfl pfl_reg, 0
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_PD_DISABLE_LPSRAM:
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/* effectively executes:
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* if (b_enable_lpsram){
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* cavs_lpsram_power_down_entire();
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* }
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*/
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beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
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m_cavs_lpsram_power_down_entire temp_reg0, temp_reg1, temp_reg2
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j _PD_DISABLE_HPSRAM
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_PD_DISABLE_HPSRAM:
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/* if value in memory pointed by pu32_hpsram_mask = 0
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(hpsram_pwrgating_mask) - do not disable hpsram. */
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beqz pu32_hpsram_mask, _PD_SLEEP
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/* effectively executes:
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* for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0;
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* --seg_index) {
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* cavs_hpsram_power_change(seg_index, mask[seg_index]);
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* }
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* where mask is given in pu32_hpsram_mask register
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*/
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.set seg_index, MAX_MEMORY_SEGMENTS - 1
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.rept MAX_MEMORY_SEGMENTS
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l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index
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m_cavs_hpsram_power_change\
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/*segment_index=*/ seg_index,\
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/*mask=*/ temp_reg0,\
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temp_reg1,\
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temp_reg2,\
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temp_reg3
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.set seg_index, seg_index - 1
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.endr
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//TODO: add LDO Control
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//TODO: add sending IPC reply from L1$ locked code
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_PD_SLEEP:
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/* effecfively executes:
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* xmp_spin()
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* waiti 5
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*/
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movi temp_reg0, 128
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loop:
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addi temp_reg0, temp_reg0, -1
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bnez temp_reg0, loop
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extw
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extw
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waiti 5
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j _PD_SLEEP
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.size power_down , . - power_down
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@ -40,8 +40,8 @@
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#include <platform/pm_runtime.h>
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#include <platform/dai.h>
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#if defined(CONFIG_APOLLOLAKE)
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//TODO: add support or at least stub api for Cannonlake & Icelake
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#if defined(CONFIG_APOLLOLAKE) || defined(CONFIG_CANNONLAKE)
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//TODO: add support or at least stub api for Icelake based on Cannonlake
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#include <platform/power_down.h>
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#endif
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@ -229,15 +229,16 @@ void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index,
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}
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}
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#if defined(CONFIG_APOLLOLAKE)
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#if defined(CONFIG_APOLLOLAKE) || defined(CONFIG_CANNONLAKE)
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void platform_pm_runtime_power_off(void)
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{
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uint32_t hpsram_mask[PLATFORM_HPSRAM_SEGMENTS];
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uint32_t hpsram_mask[PLATFORM_HPSRAM_SEGMENTS], i;
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//TODO: add LDO control for LP SRAM - set LDO BYPASS & LDO ON
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//TODO: mask to be used in the future for run-time power management of
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//SRAM banks
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//TODO: hpsram_mask to be used in the future for run-time
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//power management of SRAM banks i.e use. HPSRAM_MASK() macro
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/* power down entire HPSRAM */
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hpsram_mask[0] = 0x1;
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for (i = 0; i < PLATFORM_HPSRAM_SEGMENTS; i++)
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hpsram_mask[i] = UINT32_MAX;
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power_down(true, hpsram_mask);
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}
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|
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