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memory: connected memory max size to kconfig values 

Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This commit is contained in:
Jakub Dabek 2019-04-17 17:06:35 +02:00 committed by Tomasz Lauda
parent 738c83ddeb
commit 4c6f6f7b48
6 changed files with 9 additions and 19 deletions
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1
src/arch/xtensa/configs/suecreek_defconfig
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@ -3,3 +3,4 @@ CONFIG_CAVS_DMIC=y
CONFIG_CAVS_SSP=y
CONFIG_CORE_COUNT=4
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=47

5
src/platform/apollolake/include/platform/memory.h
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@ -282,8 +282,6 @@
#define SRAM_ALIAS_OFFSET 0x20000000
#define HP_SRAM_SIZE 0x00080000
#define SRAM_WND_BASE (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
@ -300,8 +298,6 @@
#define SRAM_ALIAS_OFFSET 0x00000000
#define HP_SRAM_SIZE 0x0001E0000
#define SRAM_WND_BASE 0xBE058000
#define HP_SRAM_VECBASE_RESET 0xBE0A0000
@ -354,7 +350,6 @@
/* LP SRAM */
#define LP_SRAM_BASE 0xBE800000
#define LP_SRAM_SIZE 0x00020000
/* Heap section sizes for module pool */
#define HEAP_RT_LP_COUNT8 0

8
src/platform/cannonlake/include/platform/memory.h
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@ -173,7 +173,6 @@
/* HP SRAM */
#define SRAM_ALIAS_OFFSET 0x20000000
#define HP_SRAM_BASE 0xBE000000
#define HP_SRAM_SIZE 0x002F0000
#define HP_SRAM_MASK 0xFF000000
/* HP SRAM Base */
@ -297,10 +296,8 @@
/* Stack configuration */
#define SOF_STACK_SIZE ARCH_STACK_SIZE
#define SOF_STACK_TOTAL_SIZE ARCH_STACK_TOTAL_SIZE
/* SOF_STACK_OFFSET defines how much memory can be power gated */
#define SOF_STACK_OFFSET 0x150000
/* SOF_STACK_BASE is moved from end of physical memory by offset */
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_STACK_OFFSET)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
@ -334,7 +331,6 @@
/* LP SRAM */
#define LP_SRAM_BASE 0xBE800000
#define LP_SRAM_SIZE 0x00020000
/* Heap section sizes for module pool */
#define HEAP_RT_LP_COUNT8 0

2
src/platform/icelake/include/platform/memory.h
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@ -176,7 +176,6 @@
/* HP SRAM */
#define SRAM_ALIAS_OFFSET 0x20000000
#define HP_SRAM_BASE 0xBE000000
#define HP_SRAM_SIZE 0x002F0000
#define HP_SRAM_MASK 0xFF000000
/* HP SRAM Base */
@ -333,7 +332,6 @@
/* LP SRAM */
#define LP_SRAM_BASE 0xBE800000
#define LP_SRAM_SIZE 0x00010000
/* Heap section sizes for module pool */
#define HEAP_RT_LP_COUNT8 0

10
src/platform/intel/cavs/include/cavs/memory.h
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@ -33,9 +33,7 @@
#include <config.h>
#define LPSRAM_BANK_SIZE (64 * 1024)
#define SRAM_BANK_SIZE LPSRAM_BANK_SIZE
#define SRAM_BANK_SIZE (64 * 1024)
#define EBB_BANKS_IN_SEGMENT 32
@ -49,6 +47,10 @@
#define MAX_MEMORY_SEGMENTS PLATFORM_HPSRAM_SEGMENTS
#define LP_SRAM_SIZE (CONFIG_LP_MEMORY_BANKS * SRAM_BANK_SIZE)
#define HP_SRAM_SIZE (CONFIG_HP_MEMORY_BANKS * SRAM_BANK_SIZE)
#define PLATFORM_HPSRAM_SEGMENTS ((PLATFORM_HPSRAM_EBB_COUNT \
+ EBB_BANKS_IN_SEGMENT - 1) / EBB_BANKS_IN_SEGMENT)
@ -57,7 +59,7 @@
#define HPSRAM_MASK(seg_idx) ((1 << (PLATFORM_HPSRAM_EBB_COUNT \
- EBB_BANKS_IN_SEGMENT * seg_idx)) - 1)
#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE)
#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * SRAM_BANK_SIZE)
#if !defined(__ASSEMBLER__) && !defined(LINKER)
void platform_init_memmap(void);

2
src/platform/suecreek/include/platform/memory.h
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@ -194,7 +194,6 @@
/* HP SRAM */
#define SRAM_ALIAS_OFFSET 0x20000000
#define HP_SRAM_BASE 0xBE000000
#define HP_SRAM_SIZE 0x002F0000 /* Should be 48 * 64 - 0x300000 ?? */
#define HP_SRAM_MASK 0xFF000000
/* HP SRAM Base */
@ -341,7 +340,6 @@
/* LP SRAM */
#define LP_SRAM_BASE 0xBE800000
#define LP_SRAM_SIZE 0x00010000
/* Heap section sizes for module pool */
#define HEAP_RT_LP_COUNT8 0