mirror of https://github.com/thesofproject/sof.git
hda-dma: utilize generic scheduling support for Link DMA
Changes implementation of HDA Link DMA to fully utilize generic scheduling support. HDA Link DMA cannot work with IRQ scheduling, so timer scheduling was hidden inside of the hda-dma driver. Now it fully utilizes timer scheduling support by default. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda
Liam Girdwood
parent
59f5fb7e5f
commit
4b821013a1
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@ -606,9 +606,9 @@ static int host_params(struct comp_dev *dev)
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}
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#endif
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/* set up callback */
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dma_set_cb(hd->dma, hd->chan, DMA_CB_TYPE_LLIST,
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host_dma_cb,
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dev);
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dma_set_cb(hd->dma, hd->chan, DMA_CB_TYPE_LLIST | DMA_CB_TYPE_PROCESS,
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host_dma_cb, dev);
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return 0;
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}
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@ -91,8 +91,6 @@
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#define HDA_DMA_MAX_CHANS 9
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#define HDA_LINK_1MS_US 1000
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#define HDA_STATE_HOST_PRELOAD BIT(0)
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#define HDA_STATE_INIT BIT(1)
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#define HDA_STATE_RELEASE BIT(2)
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@ -160,7 +158,6 @@ struct hda_chan_data {
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uint32_t period_bytes;
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uint32_t buffer_bytes;
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struct work dma_ch_work;
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#if HDA_DMA_PTR_DBG
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struct hda_dbg_data dbg_data;
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@ -270,57 +267,6 @@ static void hda_dma_get_dbg_vals(struct hda_chan_data *chan,
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#define hda_dma_ptr_trace(...)
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#endif
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static inline uint32_t hda_dma_get_data_size(struct dma *dma, uint32_t chan)
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{
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uint32_t cs;
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uint32_t bs;
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uint32_t rp;
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uint32_t wp;
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int32_t ds;
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if (chan >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, chan);
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return 0;
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}
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cs = host_dma_reg_read(dma, chan, DGCS);
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bs = host_dma_reg_read(dma, chan, DGBS);
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rp = host_dma_reg_read(dma, chan, DGBRP);
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wp = host_dma_reg_read(dma, chan, DGBWP);
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if (!(cs & DGCS_BNE))
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return 0; /* buffer is empty */
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ds = (int32_t)wp - (int32_t)rp;
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if (ds <= 0) {
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ds += bs;
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if (ds < 0) {
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trace_hddma_error("hda-dmac: %d channel %d invalid data size ds 0x%x bs 0x%x",
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dma->plat_data.id, chan, ds, bs);
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return 0;
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}
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}
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return ds;
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}
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static inline uint32_t hda_dma_get_free_size(struct dma *dma, uint32_t chan)
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{
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uint32_t bs;
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if (chan >= HDA_DMA_MAX_CHANS) {
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trace_hddma_error("hda-dmac: %d invalid channel %d",
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dma->plat_data.id, chan);
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return 0;
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}
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bs = host_dma_reg_read(dma, chan, DGBS);
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return bs - hda_dma_get_data_size(dma, chan);
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}
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static int hda_dma_host_preload(struct dma *dma, struct hda_chan_data *chan)
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{
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struct dma_sg_elem next = {
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@ -370,7 +316,7 @@ static void hda_dma_post_copy(struct dma *dma, struct hda_chan_data *chan,
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};
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if (chan->cb) {
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chan->cb(chan->cb_data, DMA_CB_TYPE_LLIST, &next);
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chan->cb(chan->cb_data, DMA_CB_TYPE_PROCESS, &next);
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if (next.size == DMA_RELOAD_END)
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/* disable channel, finished */
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hda_dma_stop(dma, chan->index);
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@ -382,26 +328,6 @@ static void hda_dma_post_copy(struct dma *dma, struct hda_chan_data *chan,
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pm_runtime_put(PM_RUNTIME_HOST_DMA_L1, 0);
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}
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static int hda_dma_tx_wait(struct dma *dma, struct hda_chan_data *chan,
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int min_bytes, uint32_t timeout_us)
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{
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uint64_t deadline = platform_timer_get(platform_timer) +
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clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) *
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timeout_us / 1000;
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while (hda_dma_get_free_size(dma, chan->index) < min_bytes) {
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if (deadline < platform_timer_get(platform_timer)) {
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trace_hddma_error("hda-dmac: %d tx timeout",
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dma->plat_data.id);
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return -ETIME;
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}
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idelay(PLATFORM_DEFAULT_DELAY);
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}
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return 0;
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}
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static int hda_dma_link_copy_ch(struct dma *dma, struct hda_chan_data *chan,
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int bytes)
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{
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@ -419,15 +345,6 @@ static int hda_dma_link_copy_ch(struct dma *dma, struct hda_chan_data *chan,
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hda_update_bits(dma, chan->index,
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DGCS, DGCS_BOR, DGCS_BOR);
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/* make sure that previous transfer is complete (playback only) */
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if (chan->direction == DMA_DIR_MEM_TO_DEV) {
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ret = hda_dma_tx_wait(dma, chan, bytes,
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PLATFORM_LINK_DMA_TIMEOUT);
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if (ret)
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goto fail;
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}
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/*
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* set BFPI to let link gateway know we have read size,
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* which will trigger next copy start.
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@ -438,7 +355,6 @@ static int hda_dma_link_copy_ch(struct dma *dma, struct hda_chan_data *chan,
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hda_dma_get_dbg_vals(chan, HDA_DBG_POST, HDA_DBG_LINK);
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hda_dma_ptr_trace(chan, "link copy", HDA_DBG_LINK);
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fail:
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return ret;
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}
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@ -504,36 +420,6 @@ static void hda_dma_enable_unlock(struct dma *dma, int channel)
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hda_dma_ptr_trace(&p->chan[channel], "enable", HDA_DBG_BOTH);
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}
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static void hda_dma_enable(struct dma *dma, int channel)
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{
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uint32_t flags;
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spin_lock_irq(&dma->lock, flags);
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hda_dma_enable_unlock(dma, channel);
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spin_unlock_irq(&dma->lock, flags);
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}
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static uint64_t hda_dma_link_work(void *data, uint64_t delay)
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{
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struct hda_chan_data *chan = (struct hda_chan_data *)data;
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/* align pointers on release */
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if (chan->state & HDA_STATE_RELEASE) {
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hda_dma_inc_link_fp(chan->dma, chan->index,
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chan->period_bytes);
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}
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if (chan->state & HDA_STATE_INIT)
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hda_dma_enable(chan->dma, chan->index);
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else
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hda_dma_link_copy_ch(chan->dma, chan, chan->period_bytes);
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/* next time to re-arm */
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return HDA_LINK_1MS_US;
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}
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/* notify DMA to copy bytes */
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static int hda_dma_link_copy(struct dma *dma, int channel, int bytes,
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uint32_t flags)
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@ -629,7 +515,6 @@ static void hda_dma_channel_put_unlocked(struct dma *dma, int channel)
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p->chan[channel].cb = NULL;
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p->chan[channel].cb_type = 0;
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p->chan[channel].cb_data = NULL;
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work_init(&p->chan[channel].dma_ch_work, NULL, NULL, 0, 0);
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}
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/* channel must not be running when this is called */
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@ -677,15 +562,6 @@ static int hda_dma_start(struct dma *dma, int channel)
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p->chan[channel].state |= HDA_STATE_INIT;
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/*
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* Activate timer if configured in cyclic mode.
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* In cyclic mode DMA start is scheduled for later,
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* to make sure we stay synchronized with the system work queue.
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*/
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if (p->chan[channel].dma_ch_work.cb)
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work_schedule_default(&p->chan[channel].dma_ch_work,
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HDA_LINK_1MS_US);
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else
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hda_dma_enable_unlock(dma, channel);
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p->chan[channel].status = COMP_STATE_ACTIVE;
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@ -768,9 +644,6 @@ static int hda_dma_stop(struct dma *dma, int channel)
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trace_hddma("hda-dmac: %d channel %d -> stop", dma->plat_data.id,
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channel);
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if (p->chan[channel].dma_ch_work.cb)
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work_cancel_default(&p->chan[channel].dma_ch_work);
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/* disable the channel */
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hda_update_bits(dma, channel, DGCS, DGCS_GEN | DGCS_FIFORDY, 0);
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p->chan[channel].status = COMP_STATE_PREPARE;
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@ -836,6 +709,14 @@ static int hda_dma_set_config(struct dma *dma, int channel,
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goto out;
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}
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if ((config->direction & (DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM)) &&
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!config->irq_disabled) {
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trace_hddma_error("hda-dmac: %d channel %d HDA Link DMA "
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"doesn't support irq scheduling");
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ret = -EINVAL;
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goto out;
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}
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/* default channel config */
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p->chan[channel].direction = config->direction;
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p->chan[channel].desc_count = config->elem_array.count;
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@ -888,12 +769,6 @@ static int hda_dma_set_config(struct dma *dma, int channel,
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p->chan[channel].period_bytes = period_bytes;
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p->chan[channel].buffer_bytes = buffer_bytes;
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/* initialize timer */
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if (config->cyclic) {
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work_init(&p->chan[channel].dma_ch_work, hda_dma_link_work,
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&p->chan[channel], WORK_HIGH_PRI, WORK_ASYNC);
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}
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/* init channel in HW */
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host_dma_reg_write(dma, channel, DGBBA, buffer_addr);
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host_dma_reg_write(dma, channel, DGBS, buffer_bytes);
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