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schedule: zephyr_dma_domain: Add macro for interrupt_clear_mask() on ARM64 

In the case of ARM64 with GIC, the interrupts are cleared after
the ISR is executed (for reference please see arm_gic_eoi() and
arch/arm64/core/isr_wrapper.S from Zephyr). Thanks to this, we
don't need to clear them explicitly, hence there's no need for
interrupt_clear_mask() to be defined. This commit fixes linkage
problems caused by the fact that interrupt_clear_mask() is not
defined on ARM64.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2023-04-19 17:09:53 +03:00 committed by Liam Girdwood
parent 05a3aa6212
commit 4a492f5439
1 changed files with 4 additions and 0 deletions
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4
src/schedule/zephyr_dma_domain.c
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@ -32,6 +32,10 @@ LOG_MODULE_DECLARE(ll_schedule, CONFIG_SOF_LOG_LEVEL);
#define interrupt_disable mux_interrupt_disable #define interrupt_disable mux_interrupt_disable
#endif #endif
#ifdef CONFIG_ARM64
#define interrupt_clear_mask(irq, bit)
#endif /* CONFIG_ARM64 */
#define SEM_LIMIT 1 #define SEM_LIMIT 1
#define ZEPHYR_PDOMAIN_STACK_SIZE 8192 #define ZEPHYR_PDOMAIN_STACK_SIZE 8192