arch: xtensa: Support wait_for_interrupt on LX6

Add LX6 version of wait_for_interrupt() as this will be needed for
cannonlake.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>

src/arch/xtensa/Makefile.am

@@ -31,7 +31,6 @@ reef_SOURCES = \
 	crt1-boards.S \
 	_vectors.S \
 	init.c \
-	wait.S \
 	timer.c \
 	task.c
 

src/arch/xtensa/include/arch/Makefile.am

@@ -4,4 +4,5 @@ noinst_HEADERS = \
 	reef.h \
 	spinlock.h \
 	task.h \
-	timer.h
+	timer.h \
+	wait.h

src/arch/xtensa/include/arch/wait.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, Intel Corporation
+ * Copyright (c) 2017, Intel Corporation
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,17 +28,42 @@
  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
  */
 
-#include <xtensa/coreasm.h>
-#include <xtensa/config/specreg.h>
-#include "xtos-internal.h"
+#include <xtensa/xtruntime.h>
 
-	.text
-	.align 4
-	.global	arch_wait_for_interrupt
-	.type	arch_wait_for_interrupt,@function
-arch_wait_for_interrupt:
-	abi_entry
-	waiti 0
-	abi_return
+#if defined(CONFIG_CANNONLAKE)
+
+static inline void arch_wait_for_interrupt(int level)
+{
+	int i;
+
+	/* this sequnce must be atomic on LX6 */
+	XTOS_SET_INTLEVEL(5);
+
+	/* LX6 needs a delay */
+	for (i = 0; i < 128; i++)
+		asm volatile("nop");
+
+	/* and to flush all loads/stores prior to wait */
+	asm volatile("isync");
+	asm volatile("extw");
+
+	/* now wait */
+	asm volatile("waiti 0");
+}
+
+#else
+
+static inline void arch_wait_for_interrupt(int level)
+{
+	 asm volatile("waiti 0");
+}
+
+#endif
+
+static inline void idelay(int n)
+{
+	while (n--) {
+		asm volatile("nop");
+	}
+}
 
-	.size	arch_wait_for_interrupt, . - arch_wait_for_interrupt

src/include/reef/wait.h

@@ -35,6 +35,7 @@
 
 #include <stdint.h>
 #include <errno.h>
+#include <arch/wait.h>
 #include <reef/debug.h>
 #include <reef/work.h>
 #include <reef/timer.h>