mirror of https://github.com/thesofproject/sof.git
arch: xtensa: Add bootloader support
Add a support for a secondary boot loader than cant be used to bootstrap multiple firmware modules. Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
This commit is contained in:
Rander Wang
Liam Girdwood
parent
aa85e2c0e9
commit
44c7093525
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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/*
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* Entry point from ROM - assumes :-
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*
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* 1) C runtime environment is initalised by ROM.
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* 2) Stack is in first HPSRAM bank.
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*/
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#include <config.h>
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#include <platform/shim.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/core-isa-boot.h>
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.type boot_pri_core, @function
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.type boot_sec_core, @function
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.begin literal_prefix .boot_entry
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.section .boot_entry.text, "ax"
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.align 4
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.global boot_entry
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boot_entry:
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entry a1, 48
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j boot_init
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.align 4
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.literal_position
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l2_mecs:
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.word SHIM_L2_MECS
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boot_init:
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.align 4
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#if defined(CONFIG_CANNONLAKE)
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/* reset memory hole */
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l32r a3, l2_mecs
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movi a5, 0
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s32i a5, a3, 0
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#endif
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#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \
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XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
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/* Enable zero-overhead loop instr buffer,
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and snoop responses, if configured. */
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movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN)
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rsr a2, MEMCTL
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or a2, a2, a3
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wsr a2, MEMCTL
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#endif
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/* determine core we are running on */
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rsr a2, PRID
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beqz a2, 1f
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/* we are seconadry core, so boot it */
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call8 boot_sec_core
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j dead
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1:
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/* we are primary core so boot it */
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call8 boot_pri_core
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dead:
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/* should never get here - we are dead */
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j dead
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.size boot_entry, . - boot_entry
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.end literal_prefix
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@ -0,0 +1,206 @@
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/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#include <arch/cache.h>
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#include <arch/wait.h>
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#include <reef/trace.h>
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#include <reef/io.h>
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#include <uapi/manifest.h>
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#include <platform/memory.h>
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/* entry point to main firmware */
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extern void _ResetVector(void);
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void boot_pri_core(void);
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void boot_sec_core(void);
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#if defined(CONFIG_CANNONLAKE)
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/* memcopy used by boot loader */
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static inline void bmemcpy(void *dest, void *src, size_t bytes)
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{
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uint32_t *d = dest;
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uint32_t *s = src;
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int i;
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for (i = 0; i < (bytes >> 2); i++)
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d[i] = s[i];
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dcache_writeback_region(dest, bytes);
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}
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/* bzero used by bootloader */
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static inline void bbzero(void *dest, size_t bytes)
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{
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uint32_t *d = dest;
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int i;
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for (i = 0; i < (bytes >> 2); i++)
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d[i] = 0;
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dcache_writeback_region(dest, bytes);
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}
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static void parse_module(struct sof_man_fw_header *hdr,
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struct sof_man_module *mod)
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{
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int i;
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uint32_t bias;
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/* each module has 3 segments */
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for (i = 0; i < 3; i++) {
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switch (mod->segment[i].flags.r.type) {
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case SOF_MAN_SEGMENT_TEXT:
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case SOF_MAN_SEGMENT_DATA:
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bias = (mod->segment[i].file_offset -
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SOF_MAN_ELF_TEXT_OFFSET);
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/* copy from IMR to SRAM */
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bmemcpy((void *)mod->segment[i].v_base_addr,
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(void *)((int)hdr + bias),
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mod->segment[i].flags.r.length * HOST_PAGE_SIZE);
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break;
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case SOF_MAN_SEGMENT_BSS:
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/* copy from IMR to SRAM */
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bbzero((void*)mod->segment[i].v_base_addr,
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mod->segment[i].flags.r.length * HOST_PAGE_SIZE);
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break;
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default:
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/* ignore */
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break;
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}
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}
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}
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/* parse FW manifest and copy modules */
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static void parse_manifest(void)
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{
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struct sof_man_fw_desc *desc =
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(struct sof_man_fw_desc *)IMR_BOOT_LDR_MANIFEST_BASE;
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struct sof_man_fw_header *hdr = &desc->header;
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struct sof_man_module *mod;
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int i;
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/* copy module to SRAM - skip bootloader module */
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for (i = 1; i < hdr->num_module_entries; i++) {
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mod = sof_man_get_module(desc, i);
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parse_module(hdr, mod);
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}
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}
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#endif
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/* power on HPSRAM */
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static int32_t hp_sram_init(void)
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{
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int delay_count = 256, timeout = 256;
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uint32_t status;
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shim_write(SHIM_LDOCTL, SHIM_HPMEM_POWER_ON);
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/* add some delay before touch power register */
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idelay(delay_count);
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/* now all the memory bank has been powered up */
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io_reg_write(HSPGCTL0, 0);
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io_reg_write(HSRMCTL0, 0);
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io_reg_write(HSPGCTL1, 0);
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io_reg_write(HSRMCTL1, 0);
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/* query the power status of first part of HP memory */
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/* to check whether it has been powered up. A few */
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/* cycles are needed for it to be powered up */
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status = io_reg_read(HSPGISTS0);
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while (status) {
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idelay(delay_count);
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status = io_reg_read(HSPGISTS0);
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if (timeout-- < 0) {
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return -EIO;
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}
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}
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/* query the power status of second part of HP memory */
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/* and do as above code */
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timeout = 256;
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status = io_reg_read(HSPGISTS1);
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while (status) {
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idelay(delay_count);
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status = io_reg_read(HSPGISTS1);
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if (timeout-- < 0) {
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return -EIO;
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}
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}
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/* add some delay before touch power register */
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idelay(delay_count);
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shim_write(SHIM_LDOCTL, SHIM_LPMEM_POWER_BYPASS);
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return 0;
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}
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/* boot secondary core - i.e core ID > 0 */
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void boot_sec_core(void)
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{
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/* TODO: prepare C stack for this core */
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while (1);
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/* now call SOF entry */
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_ResetVector();
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}
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/* boot primary core - i.e. core ID == 0 */
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void boot_pri_core(void)
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{
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int32_t result;
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/* TODO: platform trace should write to HW IPC regs on CNL */
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platform_trace_point(TRACE_BOOT_LDR_ENTRY);
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/* init the HPSRAM */
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platform_trace_point(TRACE_BOOT_LDR_HPSRAM);
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result = hp_sram_init();
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if (result < 0) {
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platform_panic(PANIC_MEM);
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return;
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}
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#if defined(CONFIG_CANNONLAKE)
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/* parse manifest and copy modules */
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platform_trace_point(TRACE_BOOT_LDR_MANIFEST);
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parse_manifest();
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#endif
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/* now call SOF entry */
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platform_trace_point(TRACE_BOOT_LDR_JUMP);
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_ResetVector();
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}
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@ -120,6 +120,22 @@ _start:
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#include "reset-unneeded.S"
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#endif
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#if XCHAL_HAVE_BOOTLOADER
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.weak _Level2FromVector
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.weak _Level3FromVector
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.weak _Level4FromVector
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.weak _Level5FromVector
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movi a4, _Level2FromVector
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wsr a4, EXCSAVE+2
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movi a4, _Level3FromVector
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wsr a4, EXCSAVE+3
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movi a4, _Level4FromVector
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wsr a4, EXCSAVE+4
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movi a4, _Level5FromVector
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wsr a4, EXCSAVE+5
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#endif
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// Initialize the stack pointer.
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// See the "ABI and Software Conventions" chapter in the
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// Xtensa ISA Reference manual for details.
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2017, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
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* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
|
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* derived from this software without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Rander Wang <rander.wang@intel.com>
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*/
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/*
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* Entry point from boot loader.
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* Fix link address of this entry to REEF_TEXT_START so that
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* it is easy for boot loader to jump to the baseFW becasue
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* the boot loader and baseFW are in different elf file.
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*/
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// Exports
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.global _MainEntry
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/**************************************************************************/
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.begin literal_prefix .MainEntry
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.section .MainEntry.text, "ax"
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.align 4
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.global _MainEntry
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_MainEntry:
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call0 _start
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.size _MainEntry, . - _MainEntry
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.end literal_prefix
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@ -35,6 +35,10 @@
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#include "xtos-internal.h"
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#include <config.h>
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#if XCHAL_HAVE_BOOTLOADER
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#include <platform/memory.h>
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#endif
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// The following reset vector avoids initializing certain registers already
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// initialized by processor reset. But it does initialize some of them
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// anyway, for minimal support of warm restart (restarting in software by
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@ -290,6 +294,7 @@ _ResetHandler:
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s32i a0, a2, 0 // clear sync variable
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.Ldonesync:
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#endif
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#if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MP_RUNSTALL
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/* On core 0, this releases other cores. On other cores this has no effect, because
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runstall control is unconnected. */
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@ -375,7 +380,6 @@ _ResetHandler:
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movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */
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cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
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#endif
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/* Now that caches are initialized, cache coherency can be enabled. */
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#if XCHAL_DCACHE_IS_COHERENT
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# if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0)
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@ -574,7 +578,15 @@ unpackdone:
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* needed (with -mlongcalls) which it doesn't with j or jx.
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* Note: This needs to be call0 regardless of the selected ABI.
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*/
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call0 _start // jump to _start (in crt1-*.S)
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#if XCHAL_HAVE_BOOTLOADER
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/*ToDo refine the _start*/
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movi a0, REEF_TEXT_START
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callx0 a0
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#else
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call0 _start // jump to _start (in crt1-*.S)
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#endif
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/* does not return */
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#else /* XCHAL_HAVE_HALT */
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