mirror of https://github.com/thesofproject/sof.git
drivers: imx: sai: specify watermark value in fifo descriptor
Specify watermark via fifo descriptor in the same way as the fifo depth is. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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d89ce5190a
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414e727a84
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@ -291,9 +291,8 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
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mask_cr5 = REG_SAI_CR5_WNW_MASK | REG_SAI_CR5_W0W_MASK |
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mask_cr5 = REG_SAI_CR5_WNW_MASK | REG_SAI_CR5_W0W_MASK |
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REG_SAI_CR5_FBT_MASK;
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REG_SAI_CR5_FBT_MASK;
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/* TODO: for the time being use half FIFO size as watermark */
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dai_update_bits(dai, REG_SAI_XCR1(REG_TX_DIR), REG_SAI_CR1_RFW_MASK,
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dai_update_bits(dai, REG_SAI_XCR1(REG_TX_DIR),
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dai->plat_data.fifo[REG_TX_DIR].watermark);
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REG_SAI_CR1_RFW_MASK, SAI_FIFO_WORD_SIZE / 2);
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dai_update_bits(dai, REG_SAI_XCR2(REG_TX_DIR), mask_cr2, val_cr2);
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dai_update_bits(dai, REG_SAI_XCR2(REG_TX_DIR), mask_cr2, val_cr2);
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dai_update_bits(dai, REG_SAI_XCR4(REG_TX_DIR), mask_cr4, val_cr4);
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dai_update_bits(dai, REG_SAI_XCR4(REG_TX_DIR), mask_cr4, val_cr4);
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dai_update_bits(dai, REG_SAI_XCR5(REG_TX_DIR), mask_cr5, val_cr5);
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dai_update_bits(dai, REG_SAI_XCR5(REG_TX_DIR), mask_cr5, val_cr5);
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@ -304,9 +303,8 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
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val_cr2 |= REG_SAI_CR2_SYNC;
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val_cr2 |= REG_SAI_CR2_SYNC;
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mask_cr2 |= REG_SAI_CR2_SYNC_MASK;
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mask_cr2 |= REG_SAI_CR2_SYNC_MASK;
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/* TODO: for the time being use half FIFO size as watermark */
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dai_update_bits(dai, REG_SAI_XCR1(REG_RX_DIR), REG_SAI_CR1_RFW_MASK,
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dai_update_bits(dai, REG_SAI_XCR1(REG_RX_DIR),
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dai->plat_data.fifo[REG_RX_DIR].watermark);
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REG_SAI_CR1_RFW_MASK, SAI_FIFO_WORD_SIZE / 2);
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dai_update_bits(dai, REG_SAI_XCR2(REG_RX_DIR), mask_cr2, val_cr2);
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dai_update_bits(dai, REG_SAI_XCR2(REG_RX_DIR), mask_cr2, val_cr2);
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dai_update_bits(dai, REG_SAI_XCR4(REG_RX_DIR), mask_cr4, val_cr4);
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dai_update_bits(dai, REG_SAI_XCR4(REG_RX_DIR), mask_cr4, val_cr4);
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dai_update_bits(dai, REG_SAI_XCR5(REG_RX_DIR), mask_cr5, val_cr5);
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dai_update_bits(dai, REG_SAI_XCR5(REG_RX_DIR), mask_cr5, val_cr5);
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@ -237,12 +237,6 @@
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#define SAI_FLAG_PMQOS BIT(0)
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#define SAI_FLAG_PMQOS BIT(0)
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#ifdef CONFIG_IMX8M
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#define SAI_FIFO_WORD_SIZE 128
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#else
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#define SAI_FIFO_WORD_SIZE 64
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#endif
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/* Divides down the audio main clock to generate the bit clock when
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/* Divides down the audio main clock to generate the bit clock when
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* configured for an internal bit clock.
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* configured for an internal bit clock.
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* The division value is (DIV + 1) * 2.
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* The division value is (DIV + 1) * 2.
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@ -50,12 +50,14 @@ static SHARED_DATA struct dai sai[] = {
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* Receive Data Registers
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* Receive Data Registers
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*/
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*/
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.depth = 64, /* in 4 bytes words */
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.depth = 64, /* in 4 bytes words */
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.watermark = 32, /* half the depth */
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.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_TX_IRQ,
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.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_TX_IRQ,
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EDMA0_SAI_CHAN_TX),
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EDMA0_SAI_CHAN_TX),
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},
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},
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = SAI_1_BASE + REG_SAI_RDR0,
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.offset = SAI_1_BASE + REG_SAI_RDR0,
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.depth = 64, /* in 4 bytes words */
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.depth = 64, /* in 4 bytes words */
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.watermark = 32, /* half the depth */
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.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_RX_IRQ,
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.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_RX_IRQ,
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EDMA0_SAI_CHAN_RX),
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EDMA0_SAI_CHAN_RX),
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},
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},
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@ -21,12 +21,14 @@ static SHARED_DATA struct dai sai[] = {
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = SAI_1_BASE + REG_SAI_TDR0,
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.offset = SAI_1_BASE + REG_SAI_TDR0,
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.depth = 128, /* in 4 bytes words */
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.depth = 128, /* in 4 bytes words */
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.watermark = 64, /* half the depth */
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/* Handshake is SDMA hardware event */
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/* Handshake is SDMA hardware event */
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.handshake = 1,
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.handshake = 1,
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},
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},
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = SAI_1_BASE + REG_SAI_RDR0,
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.offset = SAI_1_BASE + REG_SAI_RDR0,
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.depth = 128, /* in 4 bytes words */
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.depth = 128, /* in 4 bytes words */
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.watermark = 64, /* half the depth */
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.handshake = 0,
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.handshake = 0,
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},
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},
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},
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},
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@ -39,12 +41,14 @@ static SHARED_DATA struct dai sai[] = {
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.fifo[SOF_IPC_STREAM_PLAYBACK] = {
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.offset = SAI_3_BASE + REG_SAI_TDR0,
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.offset = SAI_3_BASE + REG_SAI_TDR0,
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.depth = 128, /* in 4 bytes words */
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.depth = 128, /* in 4 bytes words */
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.watermark = 64, /* half the depth */
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/* Handshake is SDMA hardware event */
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/* Handshake is SDMA hardware event */
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.handshake = 5,
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.handshake = 5,
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},
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},
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.fifo[SOF_IPC_STREAM_CAPTURE] = {
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.offset = SAI_3_BASE + REG_SAI_RDR0,
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.offset = SAI_3_BASE + REG_SAI_RDR0,
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.depth = 128, /* in 4 bytes words */
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.depth = 128, /* in 4 bytes words */
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.watermark = 64, /* half the depth */
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.handshake = 4,
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.handshake = 4,
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},
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},
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},
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},
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