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drivers: imx: sai: specify watermark value in fifo descriptor 

Specify watermark via fifo descriptor in the same way
as the fifo depth is.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This commit is contained in:
Viorel Suman 2021-06-22 12:39:45 +03:00 committed by Daniel Baluta
parent d89ce5190a
commit 414e727a84
4 changed files with 10 additions and 12 deletions
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10
src/drivers/imx/sai.c
View File

@ -291,9 +291,8 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
mask_cr5 = REG_SAI_CR5_WNW_MASK | REG_SAI_CR5_W0W_MASK |
REG_SAI_CR5_FBT_MASK;
/* TODO: for the time being use half FIFO size as watermark */
dai_update_bits(dai, REG_SAI_XCR1(REG_TX_DIR),
REG_SAI_CR1_RFW_MASK, SAI_FIFO_WORD_SIZE / 2);
dai_update_bits(dai, REG_SAI_XCR1(REG_TX_DIR), REG_SAI_CR1_RFW_MASK,
dai->plat_data.fifo[REG_TX_DIR].watermark);
dai_update_bits(dai, REG_SAI_XCR2(REG_TX_DIR), mask_cr2, val_cr2);
dai_update_bits(dai, REG_SAI_XCR4(REG_TX_DIR), mask_cr4, val_cr4);
dai_update_bits(dai, REG_SAI_XCR5(REG_TX_DIR), mask_cr5, val_cr5);
@ -304,9 +303,8 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
val_cr2 |= REG_SAI_CR2_SYNC;
mask_cr2 |= REG_SAI_CR2_SYNC_MASK;
/* TODO: for the time being use half FIFO size as watermark */
dai_update_bits(dai, REG_SAI_XCR1(REG_RX_DIR),
REG_SAI_CR1_RFW_MASK, SAI_FIFO_WORD_SIZE / 2);
dai_update_bits(dai, REG_SAI_XCR1(REG_RX_DIR), REG_SAI_CR1_RFW_MASK,
dai->plat_data.fifo[REG_RX_DIR].watermark);
dai_update_bits(dai, REG_SAI_XCR2(REG_RX_DIR), mask_cr2, val_cr2);
dai_update_bits(dai, REG_SAI_XCR4(REG_RX_DIR), mask_cr4, val_cr4);
dai_update_bits(dai, REG_SAI_XCR5(REG_RX_DIR), mask_cr5, val_cr5);

6
src/include/sof/drivers/sai.h
View File

@ -237,12 +237,6 @@
#define SAI_FLAG_PMQOS BIT(0)
#ifdef CONFIG_IMX8M
#define SAI_FIFO_WORD_SIZE 128
#else
#define SAI_FIFO_WORD_SIZE 64
#endif
/* Divides down the audio main clock to generate the bit clock when
* configured for an internal bit clock.
* The division value is (DIV + 1) * 2.

2
src/platform/imx8/lib/dai.c
View File

@ -50,12 +50,14 @@ static SHARED_DATA struct dai sai[] = {
* Receive Data Registers
*/
.depth = 64, /* in 4 bytes words */
.watermark = 32, /* half the depth */
.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_TX_IRQ,
EDMA0_SAI_CHAN_TX),
},
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = SAI_1_BASE + REG_SAI_RDR0,
.depth = 64, /* in 4 bytes words */
.watermark = 32, /* half the depth */
.handshake = EDMA_HANDSHAKE(EDMA0_SAI_CHAN_RX_IRQ,
EDMA0_SAI_CHAN_RX),
},

4
src/platform/imx8m/lib/dai.c
View File

@ -21,12 +21,14 @@ static SHARED_DATA struct dai sai[] = {
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = SAI_1_BASE + REG_SAI_TDR0,
.depth = 128, /* in 4 bytes words */
.watermark = 64, /* half the depth */
/* Handshake is SDMA hardware event */
.handshake = 1,
},
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = SAI_1_BASE + REG_SAI_RDR0,
.depth = 128, /* in 4 bytes words */
.watermark = 64, /* half the depth */
.handshake = 0,
},
},
@ -39,12 +41,14 @@ static SHARED_DATA struct dai sai[] = {
.fifo[SOF_IPC_STREAM_PLAYBACK] = {
.offset = SAI_3_BASE + REG_SAI_TDR0,
.depth = 128, /* in 4 bytes words */
.watermark = 64, /* half the depth */
/* Handshake is SDMA hardware event */
.handshake = 5,
},
.fifo[SOF_IPC_STREAM_CAPTURE] = {
.offset = SAI_3_BASE + REG_SAI_RDR0,
.depth = 128, /* in 4 bytes words */
.watermark = 64, /* half the depth */
.handshake = 4,
},
},