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topology: initial topology file for APL RVP 

It is basically copy from sof-apl-pcm512x.m4 and add hdmi support

Signed-off-by: Bard liao <bard.liao@intel.com>
This commit is contained in:
Bard liao 2018-09-27 09:02:47 +08:00
parent d40087fdd4
commit 41184b076f
2 changed files with 108 additions and 0 deletions
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2
topology/Makefile.am
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@ -31,6 +31,7 @@ MACHINES = \
sof-hsw-rt5640.tplg \
sof-apl-tdf8532.tplg \
sof-apl-pcm512x.tplg \
sof-apl-rt298.tplg \
sof-apl-wm8804.tplg \
sof-apl-da7219.tplg \
sof-glk-da7219.tplg \
@ -66,6 +67,7 @@ EXTRA_DIST = \
sof-hsw-rt5640.m4 \
sof-apl-tdf8532.m4 \
sof-apl-pcm512x.m4 \
sof-apl-rt298.m4 \
sof-apl-wm8804.m4 \
sof-apl-da7219.m4 \
sof-glk-da7219.m4 \

106
topology/sof-apl-rt298.m4 Normal file
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@ -0,0 +1,106 @@
#
# Topology for generic Apollolake UP^2 with pcm512x codec.
#
# Include topology builder
include(`utils.m4')
include(`dai.m4')
include(`pipeline.m4')
include(`ssp.m4')
include(`hda.m4')
# Include TLV library
include(`common/tlv.m4')
# Include Token library
include(`sof/tokens.m4')
# Include Apollolake DSP configuration
include(`platform/intel/bxt.m4')
#
# Define the pipelines
#
# PCM0 ----> volume -----> SSP5 (rt298)
# PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 3)
# PCM6 ----> Volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 4)
# PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 5)
#
# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1, 0, 2, s32le,
48, 1000, 0, 0)
# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
5, 5, 2, s16le,
48, 1000, 0, 0)
# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
6, 6, 2, s16le,
48, 1000, 0, 0)
# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s16le.
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
7, 7, 2, s16le,
48, 1000, 0, 0)
#
# DAIs configuration
#
# playback DAI is SSP5 using 2 periods
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
1, SSP, 5, SSP5-Codec,
PIPELINE_SOURCE_1, 2, s24le,
48, 1000, 0, 0)
# playback DAI is iDisp1 using 2 periods
# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
5, HDA, 3, iDisp1,
PIPELINE_SOURCE_5, 2, s32le,
48, 1000, 0, 0)
# playback DAI is iDisp2 using 2 periods
# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
6, HDA, 4, iDisp2,
PIPELINE_SOURCE_6, 2, s32le,
48, 1000, 0, 0)
# playback DAI is iDisp3 using 2 periods
# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-playback.m4,
7, HDA, 5, iDisp3,
PIPELINE_SOURCE_7, 2, s32le,
48, 1000, 0, 0)
# PCM Low Latency, id 0
PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1)
PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_5)
PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_6)
PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_7)
#
# BE configurations - overrides config in ACPI if present
#
#
# 3 HDMI/DP outputs (ID: 3,4,5)
DAI_CONFIG(SSP, 5, 0, SSP5-Codec,
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
SSP_CLOCK(bclk, 3072000, codec_slave),
SSP_CLOCK(fsync, 48000, codec_slave),
SSP_TDM(2, 32, 3, 3),
SSP_CONFIG_DATA(SSP, 5, 24)))
HDA_DAI_CONFIG(3, 3, iDisp1)
HDA_DAI_CONFIG(4, 4, iDisp2)
HDA_DAI_CONFIG(5, 5, iDisp3)