mirror of https://github.com/thesofproject/sof.git
ipc4: add fw_reg definition
fw_reg is located in memory windows 0 for host to query fw status Signed-off-by: Rander Wang <rander.wang@intel.com>
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2021 Intel Corporation. All rights reserved.
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*/
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/*
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* This file contains structures that are exact copies of an existing ABI used
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* by IOT middleware. They are Intel specific and will be used by one middleware.
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*
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* Some of the structures may contain programming implementations that makes them
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* unsuitable for generic use and general usage.
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*
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* This code is mostly copied "as-is" from existing C++ interface files hence the use of
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* different style in places. The intention is to keep the interface as close as possible to
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* original so it's easier to track changes with IPC host code.
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*/
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/**
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* \file include/ipc4/fw_reg.h
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* \brief IPC4 fw registers in mailbox for host
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* NOTE: This ABI uses bit fields and is non portable.
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*/
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#ifndef __IPC4_FW_REG_H__
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#define __IPC4_FW_REG_H__
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#include <stdint.h>
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#include <ipc4/module.h>
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#include <platform/lib/cpu.h>
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#include <platform/lib/dma.h>
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struct ipc4_fw_status_reg {
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uint32_t state : 28;
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/* Last module ID updated FSR */
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uint32_t module : 3;
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/* State of DSP core */
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uint32_t running : 1;
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} __attribute__((packed, aligned(4)));
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typedef uint32_t ipc4_last_error;
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struct ipc4_fw_pwr_status {
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/* currently set astate */
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uint32_t curr_astate : 4;
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/* cached IMR usage status for previous D0i3 */
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uint32_t cached_imr_usage_status : 1;
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uint32_t curr_fstate : 3;
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uint32_t wake_tick_period : 5;
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uint32_t active_pipelines_count : 6;
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uint32_t rsvd0 : 13;
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} __attribute__((packed, aligned(4)));
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struct ipc4_pipeline_registers {
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/**
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* Stream start offset (LPIB) reported by mixin module allocated on pipeline attached
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* to Host Output Gateway when first data is being mixed to mixout module. When data
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* is not mixed (right after creation/after reset) value "(uint64_t)-1" is reported.
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* In number of bytes.
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* */
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uint64_t stream_start_offset;
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/**
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* Stream end offset (LPIB) reported by mixin module allocated on pipeline attached
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* to Host Output Gateway during transition from RUNNING to PAUSED. When data
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* is not mixed (right after creation/after reset) value "(uint64_t)-1" is reported. When
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* first data is mixed then value "0"is reported.
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* In number of bytes.
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* */
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uint64_t stream_end_offset;
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} __attribute__((packed, aligned(8)));
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#define IPC4_PV_MAX_SUPPORTED_CHANNELS 8
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struct ipc4_peak_volume_regs {
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uint32_t peak_meter_[IPC4_PV_MAX_SUPPORTED_CHANNELS];
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uint32_t current_volume_[IPC4_PV_MAX_SUPPORTED_CHANNELS];
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uint32_t target_volume_[IPC4_PV_MAX_SUPPORTED_CHANNELS];
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} __attribute__((packed, aligned(4)));
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struct ipc4_llp_reading {
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/* lower part of 64-bit LLP */
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uint32_t llp_l;
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/* upper part of 64-bit LLP */
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uint32_t llp_u;
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/* lower part of 64-bit Wallclock */
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uint32_t wclk_l;
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/* upper part of 64-bit Wallclock */
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uint32_t wclk_u;
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} __attribute__((packed, aligned(4)));
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struct ipc4_llp_reading_slot {
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uint32_t node_id;
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struct ipc4_llp_reading reading;
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} __attribute__((packed, aligned(4)));
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union ipc4_rom_info {
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struct {
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uint32_t fuse_values: 8;
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uint32_t load_method: 1;
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uint32_t downlink_IPC_use_DMA: 1;
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uint32_t load_method_reserved: 2;
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uint32_t implementation_revision_min: 4;
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uint32_t implementation_revision_maj: 4;
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uint32_t implementation_version_min: 4;
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uint32_t implementation_version_maj: 4;
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uint32_t reserved : 4;
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} bits;
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struct {
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uint32_t rsvd1: 16;
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uint32_t type: 12;
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uint32_t rsvd2: 4;
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} platform;
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} __attribute__((packed, aligned(4)));
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struct ipc4_fw_registers {
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struct ipc4_fw_status_reg fsr;
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ipc4_last_error lec;
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struct ipc4_fw_pwr_status fps;
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uint32_t mem_status;
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uint32_t ltr;
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uint32_t rsvd0;
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union ipc4_rom_info rom_info;
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uint32_t rsvd1[5];
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uint32_t dbg_log_wp[MAX_CORE_COUNT];
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uint32_t rsvd2[4 - MAX_CORE_COUNT];
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struct ipc4_pipeline_registers pipeline_regs[PLATFORM_MAX_DMA_CHAN];
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struct ipc4_peak_volume_regs peak_vol_regs[10];
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struct ipc4_llp_reading_slot llp_gpdma_reading_slots[MAX_GPDMA_COUNT * 8];
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struct ipc4_llp_reading_slot llp_sndw_reading_slots[MAX_GPDMA_COUNT * 8];
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uint32_t memory_window_2_slot_desc[IPC4_MAX_SUPPORTED_LIBRARIES];
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} __attribute__((packed, aligned(4)));
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#endif
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@ -26,6 +26,12 @@
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#include <stdint.h>
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/* TODO: revisit it. Now it aligns with audio sdk
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* and we will update this value and sdk when more
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* libraries are supported
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*/
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#define IPC4_MAX_SUPPORTED_LIBRARIES 16
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#define SOF_IPC4_DST_QUEUE_ID_BITFIELD_SIZE 3
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#define SOF_IPC4_SRC_QUEUE_ID_BITFIELD_SIZE 3
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