mirror of https://github.com/thesofproject/sof.git
byt, hsw: call arch_interrupt_clear() directly
Platform interrupt handling code should call arch_interrupt_clear() directly, no need to use the interrupt_clear() wrapper. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
parent
0e80be7d52
commit
31cf4f084b
|
@ -29,40 +29,40 @@ void platform_interrupt_clear(uint32_t irq, uint32_t mask)
|
||||||
switch (irq) {
|
switch (irq) {
|
||||||
case IRQ_NUM_EXT_SSP0:
|
case IRQ_NUM_EXT_SSP0:
|
||||||
shim_write(SHIM_PISR, mask << 3);
|
shim_write(SHIM_PISR, mask << 3);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_SSP1:
|
case IRQ_NUM_EXT_SSP1:
|
||||||
shim_write(SHIM_PISR, mask << 4);
|
shim_write(SHIM_PISR, mask << 4);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_SSP2:
|
case IRQ_NUM_EXT_SSP2:
|
||||||
shim_write(SHIM_PISR, mask << 5);
|
shim_write(SHIM_PISR, mask << 5);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_DMAC0:
|
case IRQ_NUM_EXT_DMAC0:
|
||||||
shim_write(SHIM_PISR, mask << 16);
|
shim_write(SHIM_PISR, mask << 16);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_DMAC1:
|
case IRQ_NUM_EXT_DMAC1:
|
||||||
shim_write(SHIM_PISR, mask << 24);
|
shim_write(SHIM_PISR, mask << 24);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
#if defined CONFIG_CHERRYTRAIL
|
#if defined CONFIG_CHERRYTRAIL
|
||||||
case IRQ_NUM_EXT_DMAC2:
|
case IRQ_NUM_EXT_DMAC2:
|
||||||
shim_write(SHIM_PISRH, mask << 0);
|
shim_write(SHIM_PISRH, mask << 0);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_SSP3:
|
case IRQ_NUM_EXT_SSP3:
|
||||||
shim_write(SHIM_PISRH, mask << 8);
|
shim_write(SHIM_PISRH, mask << 8);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_SSP4:
|
case IRQ_NUM_EXT_SSP4:
|
||||||
shim_write(SHIM_PISRH, mask << 9);
|
shim_write(SHIM_PISRH, mask << 9);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
case IRQ_NUM_EXT_SSP5:
|
case IRQ_NUM_EXT_SSP5:
|
||||||
shim_write(SHIM_PISRH, mask << 10);
|
shim_write(SHIM_PISRH, mask << 10);
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -32,7 +32,7 @@ void platform_interrupt_clear(uint32_t irq, uint32_t mask)
|
||||||
case IRQ_NUM_EXT_DMAC1:
|
case IRQ_NUM_EXT_DMAC1:
|
||||||
case IRQ_NUM_EXT_SSP0:
|
case IRQ_NUM_EXT_SSP0:
|
||||||
case IRQ_NUM_EXT_SSP1:
|
case IRQ_NUM_EXT_SSP1:
|
||||||
interrupt_clear(irq);
|
arch_interrupt_clear(irq);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Reference in New Issue