OrgACRN
/
sof
mirror of https://github.com/thesofproject/sof.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

arch: extensa: cpu: reset stale trace point during power down 

When a secondary core is disabled and re-enabled without a
D3 cycle, the POWER_UP IDC message end up reading the trace
point message from the first boot. Reset it during power down
to avoid this.

Suggested-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
This commit is contained in:
Ranjani Sridharan 2021-06-22 23:39:13 -07:00 committed by Liam Girdwood
parent 7b06921b6b
commit 29f0aeb913
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/xtensa/lib/cpu.c
View File

@ -180,6 +180,8 @@ void cpu_power_down_core(void)
pm_runtime_put(PM_RUNTIME_DSP, PWRD_BY_TPLG | cpu_get_id());
trace_point(0);
/* arch_wait_for_interrupt() not used, because it will cause panic.
* This code is executed on irq lvl > 0, which is expected.
* Core will be put into reset by host anyway.