mirror of https://github.com/thesofproject/sof.git
drivers: mtk: add mt8188 AFE sinegen support
Add MT8188 sinegen driver for debug purpose. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
This commit is contained in:
Trevor Wu
Liam Girdwood
parent
d1dd69822e
commit
2633535cb2
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@ -4,6 +4,9 @@ add_local_sources(sof afe-memif.c afe-dai.c afe-drv.c)
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if(CONFIG_MT8186)
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add_subdirectory(mt8186)
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endif()
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if(CONFIG_MT8188)
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add_subdirectory(mt8188)
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endif()
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if(CONFIG_MT8195)
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add_subdirectory(mt8195)
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endif()
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: BSD-3-Clause
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if(CONFIG_TEST_SGEN)
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add_local_sources(sof afe-sgen.c)
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endif()
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@ -0,0 +1,258 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2023 MediaTek. All rights reserved.
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*
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* Author: Trevor Wu <trevor.wu@mediatek.com>
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*/
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#include <stdint.h>
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#include <sof/drivers/afe-sgen.h>
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#include <sof/lib/io.h>
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#include <sof/lib/uuid.h>
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#include <sof/trace/trace.h>
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#include <mt8188-afe-reg.h>
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#include <mt8188-afe-common.h>
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/* 99316bd9-07b9-4665-8179-6e048d67cb45 */
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DECLARE_SOF_UUID("sgen", sgen_uuid, 0x99316bd9, 0x07b9, 0x4665,
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0x81, 0x79, 0x6e, 0x04, 0x8d, 0x67, 0xcb, 0x45);
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DECLARE_TR_CTX(sgen_tr, SOF_UUID(sgen_uuid), LOG_LEVEL_INFO);
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/*
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* Note: TEST_SGEN for test only
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* Define this TEST_SGEN to enable sine tone generator
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* then output data to audio memory interface(memif),
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* you can set TEST_SGEN_ID to choose output to which memif.
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* e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8186_MEMIF_DL2",
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* the data source of DL2 will from sine generator.
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*/
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#define TEST_SGEN_ID MT8188_MEMIF_DL2
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#define AUDIO_TML_PD_MASK 1
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#define AUDIO_TML_PD_SHIFT 27
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#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f
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#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0
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#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f
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#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12
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#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7
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#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5
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#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7
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#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17
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#define AFE_SGEN_MUTE_CH1_MASK 0x1
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#define AFE_SGEN_MUTE_CH1_SHIFT 24
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#define AFE_SGEN_MUTE_CH2_MASK 0x1
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#define AFE_SGEN_MUTE_CH2_SHIFT 25
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#define AFE_SGEN_ENABLE_MASK 0x1
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#define AFE_SGEN_ENABLE_SHIFT 26
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#define AFE_SINEGEN_CON1_TIMING_CH1_MASK 0x1f
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#define AFE_SINEGEN_CON1_TIMING_CH1_SHIFT 16
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#define AFE_SINEGEN_CON1_TIMING_CH2_MASK 0x1f
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#define AFE_SINEGEN_CON1_TIMING_CH2_SHIFT 21
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#define AFE_SINEGEN_LB_MODE_MSK 0xff
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#define AFE_SINEGEN_LB_MODE_SHIFT 24
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enum {
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MT8188_SGEN_UL5 = 0x18,
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MT8188_SGEN_UL4 = 0x1f,
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MT8188_SGEN_DL3 = 0x47,
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MT8188_SGEN_DL2 = 0x60,
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};
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/*sgen freq div*/
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enum {
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SGEN_FREQ_64D1 = 1,
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SGEN_FREQ_64D2 = 2,
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SGEN_FREQ_64D3 = 3,
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SGEN_FREQ_64D4 = 4,
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SGEN_FREQ_64D5 = 5,
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SGEN_FREQ_64D6 = 6,
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SGEN_FREQ_64D7 = 7,
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SGEN_FREQ_64D8 = 8,
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};
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/*sgen amp div*/
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enum {
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SGEN_AMP_D1 = 0,
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SGEN_AMP_D2 = 1,
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SGEN_AMP_D4 = 2,
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SGEN_AMP_D8 = 3,
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SGEN_AMP_D16 = 4,
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SGEN_AMP_D32 = 5,
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SGEN_AMP_D64 = 6,
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SGEN_AMP_D128 = 7,
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};
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enum {
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SGEN_CH_TIMING_8K = 0,
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SGEN_CH_TIMING_12K = 1,
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SGEN_CH_TIMING_16K = 2,
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SGEN_CH_TIMING_24K = 3,
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SGEN_CH_TIMING_32K = 4,
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SGEN_CH_TIMING_48K = 5,
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SGEN_CH_TIMING_96K = 6,
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SGEN_CH_TIMING_192K = 7,
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SGEN_CH_TIMING_384K = 8,
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SGEN_CH_TIMING_7P35K = 16,
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SGEN_CH_TIMING_11P025K = 17,
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SGEN_CH_TIMING_14P7K = 18,
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SGEN_CH_TIMING_22P05K = 19,
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SGEN_CH_TIMING_29P4K = 20,
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SGEN_CH_TIMING_44P1K = 21,
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SGEN_CH_TIMING_88P2K = 22,
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SGEN_CH_TIMING_176P4K = 23,
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SGEN_CH_TIMING_352P8K = 24,
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};
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static uint32_t mt8188_sinegen_timing(uint32_t rate)
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{
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uint32_t sinegen_timing;
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switch (rate) {
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case 8000:
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sinegen_timing = SGEN_CH_TIMING_8K;
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break;
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case 12000:
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sinegen_timing = SGEN_CH_TIMING_12K;
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break;
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case 16000:
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sinegen_timing = SGEN_CH_TIMING_16K;
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break;
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case 24000:
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sinegen_timing = SGEN_CH_TIMING_24K;
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break;
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case 32000:
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sinegen_timing = SGEN_CH_TIMING_32K;
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break;
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case 48000:
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sinegen_timing = SGEN_CH_TIMING_48K;
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break;
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case 96000:
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sinegen_timing = SGEN_CH_TIMING_96K;
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break;
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case 192000:
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sinegen_timing = SGEN_CH_TIMING_192K;
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break;
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case 384000:
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sinegen_timing = SGEN_CH_TIMING_384K;
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break;
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case 7350:
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sinegen_timing = SGEN_CH_TIMING_7P35K;
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break;
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case 11025:
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sinegen_timing = SGEN_CH_TIMING_11P025K;
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break;
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case 22050:
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sinegen_timing = SGEN_CH_TIMING_22P05K;
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break;
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case 44100:
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sinegen_timing = SGEN_CH_TIMING_44P1K;
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break;
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case 88200:
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sinegen_timing = SGEN_CH_TIMING_88P2K;
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break;
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case 176400:
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sinegen_timing = SGEN_CH_TIMING_176P4K;
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break;
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case 352800:
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sinegen_timing = SGEN_CH_TIMING_352P8K;
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break;
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default:
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sinegen_timing = SGEN_CH_TIMING_48K;
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tr_err(&sgen_tr, "invalid rate %d, set default 48k ", rate);
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}
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tr_dbg(&sgen_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing);
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return sinegen_timing;
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}
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static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift)
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{
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io_reg_update_bits(AFE_BASE_ADDR + addr_offset, mask << shift, val << shift);
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}
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static uint32_t mtk_afe_reg_read(uint32_t addr_offset)
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{
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return io_reg_read(AFE_BASE_ADDR + addr_offset);
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}
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static void mt8188_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable)
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{
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uint32_t loopback_mode, reg_1, reg_2, sinegen_timing;
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tr_dbg(&sgen_tr, "sgen_id %d, enable %d", sgen_id, enable);
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sinegen_timing = mt8188_sinegen_timing(rate);
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if (enable == 1) {
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/* set loopback mode */
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switch (sgen_id) {
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case MT8188_MEMIF_UL4:
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loopback_mode = MT8188_SGEN_UL4;
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break;
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case MT8188_MEMIF_UL5:
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loopback_mode = MT8188_SGEN_UL5;
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break;
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case MT8188_MEMIF_DL2:
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loopback_mode = MT8188_SGEN_DL2;
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break;
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case MT8188_MEMIF_DL3:
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loopback_mode = MT8188_SGEN_DL3;
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break;
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default:
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tr_err(&sgen_tr, "invalid sgen_id %d", sgen_id);
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return;
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}
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/* enable sinegen clock*/
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mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT);
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/*loopback source*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON2, AFE_SINEGEN_LB_MODE_MSK, loopback_mode,
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AFE_SINEGEN_LB_MODE_SHIFT);
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/* sine gen timing*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH1_MASK,
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sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH1_SHIFT);
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH2_MASK,
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sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH2_SHIFT);
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/*freq div*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK,
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SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT);
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK,
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SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT);
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/*amp div*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2,
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AFE_SGEN_AMP_DIV_CH1_SHIFT);
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2,
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AFE_SGEN_AMP_DIV_CH2_SHIFT);
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/* enable sgen*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 1,
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AFE_SGEN_ENABLE_SHIFT);
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} else {
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/* disable sgen*/
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mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 0,
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AFE_SGEN_ENABLE_SHIFT);
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/* disable sgen clock */
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mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT);
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}
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reg_1 = mtk_afe_reg_read(AFE_SINEGEN_CON0);
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reg_2 = mtk_afe_reg_read(AFE_SINEGEN_CON2);
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tr_dbg(&sgen_tr, "AFE_SINEGEN_CON0 0x%x, AFE_SINEGEN_CON2 0x%x", reg_1, reg_2);
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}
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void afe_sinegen_enable(void)
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{
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mt8188_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1);
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}
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void afe_sinegen_disable(void)
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{
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mt8188_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0);
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}
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